Gert Goossens - researchr alias

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Viewing Publication 1 - 39 from 39

2015

ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfacesRoberto Ammendola, Andrea Biagioni, Ottorino Frezza, Werner Geurts, Gert Goossens, Francesca Lo Cicero, Alessandro Lonardo, Pier Stanislao Paolucci, Davide Rossetti, Francesco Simula, Laura Tosoratto, Piero Vicini. fgcs, 53:109-118, 2015. [doi]

2007

Multi-ASIP SoCs - or how to design ultra-low power architectures for wireless and multi-media systemsGert Goossens. issoc 2007: 1 [doi]

2006

Design of ASIPs in multi-processor SoCs using the Chess/Checkers retargetable tool suiteGert Goossens, Dirk Lanneer, Werner Geurts, Johan Van Praet. issoc 2006: 1-4 [doi]

2001

Processor modeling and code selection for retargetable compilationJohan Van Praet, Dirk Lanneer, Werner Geurts, Gert Goossens. todaes, 6(3):277-307, 2001. [doi]

1997

1996

A Graph Based Processor Model for Retargetable Code GenerationJohan Van Praet, Dirk Lanneer, Gert Goossens, Werner Geurts, Hugo De Man. date 1996: 102-107 [doi]

1995

1994

Software Synthesis for real-time information processing systemsMarco Cornero, Filip Thoen, Gert Goossens, Francesco Curatelli. Dagstuhl 1995: 260-279

Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line OptimizationFrancis Depuydt, Werner Geurts, Gert Goossens, Hugo De Man. eurodac 1994: 490-494

Scheduling with register constraints for DSP architecturesFrancis Depuydt, Gert Goossens, Hugo De Man. integration, 18(1):95-120, 1994. [doi]

Design of heterogeneous ICs for mobile and personal communication systemsGert Goossens, Ivo Bolsens, Bill Lin, Francky Catthoor. iccad 1994: 524-531 [doi]

Chess: retargetable code generation for embedded DSP processorsDirk Lanneer, Johan Van Praet, Augusli Kifli, Koen Schoofs, Werner Geurts, Filip Thoen, Gert Goossens. Dagstuhl 1995: 85-102

Data routing: a paradigm for efficient data-path synthesis and code generationDirk Lanneer, Marco Cornero, Gert Goossens, Hugo De Man. isss 1994: 17-22 [doi]

Instruction set definition and instruction selection for ASIPsJohan Van Praet, Gert Goossens, Dirk Lanneer, Hugo De Man. isss 1994: 11-16 [doi]

Signal Type Optimisation in the Design of Time-Multiplexed DSP ArchitecturesKoen Schoofs, Gert Goossens, Hugo De Man. eurodac 1994: 502-506

Bit-alignment for retargetable code generatorsKoen Schoofs, Gert Goossens, Hugo De Man. isss 1994: 76-81 [doi]

A generalized state assignment theory for transformations on signal transition graphsPeter Vanbekbergen, Bill Lin, Gert Goossens, Hugo De Man. vlsisp, 7(1-2):101-115, 1994. [doi]

1993

High-level synthesis for real-time digital signal processingJan Vanhoof, Karl van Rompaey, Ivo Bolsens, Gert Goossens, Hugo De Man. Volume 216 of The Kluwer international series in engineering and computer science, Kluwer, 1993.

1992

Flag/Condition Handling and Branch Assignment for Large Microcoded ControllersAugusli Kifli, R. De Wulf, J. Zegers, Gert Goossens, Paul Six, Hugo De Man. ifip10-2 1993: 61-71

Combined hardware selection and pipelining in high-performance data-path designStefaan Note, Francky Catthoor, Gert Goossens, Hugo De Man. tcad, 11(4):413-423, 1992. [doi]

Models for bit-true simulation and high-level synthesis of DSP applicationsMarc Pauwels, Dirk Lanneer, Francky Catthoor, Gert Goossens, Hugo De Man. glvlsi 1992: 52-59 [doi]

A generalized state assignment theory for transformation on signal transition graphsPeter Vanbekbergen, Bill Lin, Gert Goossens, Hugo De Man. iccad 1992: 112-117 [doi]

Optimized synthesis of asynchronous control circuits from graph-theoretic specificationsPeter Vanbekbergen, Gert Goossens, Francky Catthoor, Hugo De Man. tcad, 11(11):1426-1438, 1992. [doi]

1991

Clustering Techniques for Register Optimization During Scheduling PreprocessingFrancis Depuydt, Gert Goossens, Hugo De Man. iccad 1991: 280-283

1990

An efficient microcode compiler for application specific DSP processorsGert Goossens, Jan M. Rabaey, Joos Vandewalle, Hugo De Man. tcad, 9(9):925-937, 1990. [doi]

Open-ended system for high-level synthesis of flexible signal processorsDirk Lanneer, Francky Catthoor, Gert Goossens, Marc Pauwels, Jef L. van Meerbergen, Hugo De Man. eurodac 1990: 272-276 [doi]

Architecture-driven synthesis techniques for VLSI implementation of DSP algorithmsHugo De Man, Francky Catthoor, Gert Goossens, Jan Vanhoof, Jef L. van Meerbergen, Stefaan Note, Jos A. Huisken. pieee, 78(2):319-335, 1990. [doi]

Combined hardware selection and pipelining in high performance data-path designStefaan Note, Francky Catthoor, Gert Goossens, Hugo De Man. iccd 1990: 328-331 [doi]

An integrated automatic design system for complex DSP algorithmsJef L. van Meerbergen, Jos Huisken, Paul E. R. Lippens, O. McArdle, R. Segers, Gert Goossens, J. Vanhoof, Dirk Lanneer, Francky Catthoor, Hugo De Man. vlsisp, 1(4):265-278, 1990. [doi]

Optimized Synthesis of Asynchronous Control Circuits from Graph-Theoretic SpecificationsPeter Vanbekbergen, Francky Catthoor, Gert Goossens, Hugo De Man. iccad 1990: 184-187

1989

Loop Optimization in Register-Transfer Scheduling for DSP-SystemsGert Goossens, Joos Vandewalle, Hugo De Man. dac 1989: 826-831 [doi]

1988

Architectural strategies for an application-specific synchronous multiprocessor environmentFrancky Catthoor, Jan M. Rabaey, Gert Goossens, Jef L. van Meerbergen, Rajeev Jain, Hugo J. De Man, Joos Vandewalle. tsp, 36(2):265-284, 1988. [doi]

1985

CAD Tools for the optimized design of custom VLSI wave digital filtersRajeev Jain, Gert Goossens, Luc J. M. Claesen, Joos Vandewalle, Hugo De Man, L. Gazsi, A. Fettweis. icassp 1985: 1465-1468 [doi]

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Publications by 'Gert Goossens'

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2015

2007

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1996

1995

1994

1993

1992

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1990

1989

1988

1985

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