Table of Contents

• RATAN: A tool for rate analysis and rate constraint debugging for embedded systemsAli Dasdan, Anmol Mathur, Rajesh K. Gupta. 2-6 [doi]
• Efficient utilization of scratch-pad memory in embedded processor applicationsPreeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau. 7-11 [doi]
• Interface timing verification with delay correlation using constraint logic programmingPierre Girodias, Eduard Cerny. 12-19 [doi]
• Sequential circuit test generation using dynamic state traversalMichael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel. 22-28 [doi]
• MOSAIC: a multiple-strategy oriented sequential ATPG for integrated circuitsA. Dargelas, C. Gauthron, Yves Bertrand. 29-36 [doi]
• New static compaction techniques of test sequences for sequential circuitsFulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda. 37-43 [doi]
• A methodology for designing continuous-time sigma-delta modulatorsPhilippe Bénabès, Mansour Keramat, Richard Kielbasa. 46-50 [doi]
• A CMOS low-voltage, high-gain op-ampGuo-Neng Lu, Gerard Sou. 51-55 [doi]
• High-level synthesis of analog sensor interface front-endsStéphane Donnay, Georges G. E. Gielen, Willy M. C. Sansen, Wim Kruiskamp, Domine Leenaerts, W. van Bokhoven. 56-60 [doi]
• Structural BIST insertion using behavioral test analysisMehrdad Nourani, Christos A. Papachristou. 64-68 [doi]
• On the generation of pseudo-deterministic two-patterns test sequence with LFSRsChristian Dufaza, Yervant Zorian. 69-76 [doi]
• Cellular automata for generating deterministic test sequencesDimitrios Kagaris, Spyros Tragoudas. 77-81 [doi]
• Fast controllers for data dominated applicationsAndre Hertwig, Hans-Joachim Wunderlich. 84-89 [doi]
• Random benchmark circuits with controlled attributesKazuo Iwama, Kensuke Hino, Hiroyuki Kurokawa, Sunao Sawada. 90-97 [doi]
• Technology mapping of speed-independent circuits based on combinational decomposition and resynthesisJordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev. 98-105 [doi]
• Generation of the HDL-A-model of a micromembrane from its finite-element-descriptionKlaus Hofmann, Manfred Glesner, Nicu Sebe, A. Manolescu, Santiago Marco, Josep Samitier, Jean-Michel Karam, Bernard Courtois. 108-112 [doi]
• Microsystem design using simulator couplingS. Wünsche, C. Clauss, P. Schwarz, Frank Winkler. 113-118 [doi]
• Modeling and simulation of electromechanical transducers in microsystems using an analog hardware description languageB. Romanowicz, M. Laudon, P. Lerch, P. Renaud, Hans Peter Amann, A. Boegli, Vincent Moser, Fausto Pellandini. 119-123 [doi]
• Delay management for programmable video signal processorsM. L. G. Smeets, Emile H. L. Aarts, Gerben Essink, Erwin A. de Kock. 126-133 [doi]
• Hierarchical scheduling and allocation of multirate systems on heterogeneous multiprocessorsYanbing Li, Wayne Wolf. 134-139 [doi]
• Retargetable generation of code selectors from HDL processor modelsRainer Leupers, Peter Marwedel. 140-144 [doi]
• An RTL methodology to enable low overhead combinational testingSubhrajit Bhattacharya, Sujit Dey, Bhaskar Sengupta. 146-152 [doi]
• A controller testability analysis and enhancement techniqueXinli Gu, Erik Larsson, Krzysztof Kuchcinski, Zebo Peng. 153-157 [doi]
• Analyzing testability from behavioral to RT levelMarie-Lise Flottes, R. Pires, Bruno Rouzeyre. 158-165 [doi]
• Fast and efficient construction of BDDs by reordering based synthesisAndreas Hett, Rolf Drechsler, Bernd Becker. 168-175 [doi]
• Verification and synthesis of counters based on symbolic techniquesGianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Stefano Quer. 176-181 [doi]
• Using MTBDDs for discrete timed symbolic model checkingThomas Kropf, Jürgen Ruf. 182-187 [doi]
• Analysis of 3D conjugate heat transfers in electronicsJ. P. Fradin, L. Molla, B. Desaunettes. 190-194 [doi]
• Smart sensor system application: an integrated compassRonald J. W. T. Tangelder, G. Diemel, Hans G. Kerkhoff. 195-199 [doi]
• Automatic transfer of parametric FEM models into CAD-layout formats for top-down design of microsystemsM. Lang, D. David, Manfred Glesner. 200-204 [doi]
• Highly scalable parallel parametrizable architecture of the motion estimatorRadim Cmar, Serge Vernalde. 208-212 [doi]
• Design and implementation of a coprocessor for cryptography applicationsAnder Royo, Javier Moran, Juan Carlos López. 213-217 [doi]
• On the way to the 2.5 Gbits/s ATM network ATM multiplexer demultiplexer ASICJ. Riesco, J. C. Diaz, L. A. Merayo, J. L. Conesa, C. Santos, E. Juarez. 218-222 [doi]
• Solving graph optimization problems with ZBDDsOlivier Coudert. 224-228 [doi]
• Minimizing ROBDD sizes of incompletely specified Boolean functionsby exploiting strong symmetriesChristoph Scholl, S. Melchior, Günter Hotz, Paul Molitor. 229-234 [doi]
• Connection error location and correction in combinational circuitsAyman M. Wahba, Dominique Borrione. 235-241 [doi]
• Shaping a VLSI wire to minimize Elmore delayJohn P. Fishburn. 244-251 [doi]
• Inductance analysis of on-chip interconnects [deep submicron CMOS]Sandip Kundu, Uttam Ghoshal. 252-255 [doi]
• Cartesian multipole based numerical integration for 3D capacitance extractionU. Geigenmüller, N. P. van der Meijs. 256-259 [doi]
• CCII+ current conveyor based BIC monitor for I::DDQ:: testing of complex CMOS circuitsViera Stopjaková, Hans A. R. Manhaeve. 266-270 [doi]
• Deep sub-micron I::DDQ:: testing: issues and solutionsM. Sachdev. 271-278 [doi]
• A production-oriented measurement method for fast and exhaustive Iddq testsB. Laquai, H. Richter, H. Werkmann. 279-286 [doi]
• Library mapping for memoriesPradip K. Jha, Nikil D. Dutt. 288-292 [doi]
• Architectural exploration and optimization for counter based hardware address generationMiguel Miranda, M. Kaspar, Francky Catthoor, Hugo De Man. 293-298 [doi]
• RTL synthesis with physical and controller informationMin Xu, Fadi J. Kurdahi. 299-303 [doi]
• Two-way partitioning based on direction vector [layout design]K. S. Seong, C. M. Kyung. 306-310 [doi]
• Multi-layer chip-level global routing using an efficient graph-based Steiner tree heuristicLe-Chin Eugene Liu, Carl Sechen. 311-318 [doi]
• A gridless multi-layer router for standard cell circuits using CTM cellsHsiao-Ping Tseng, Carl Sechen. 319-326 [doi]
• A programmable boundary scan technique for board-level, parallel functional duplex march testing of word-oriented multiport static RAMsKanad Chakraborty, Pinaki Mazumder. 330-334 [doi]
• Fault-secure shifter design: results and implementationsRicardo de Oliveira Duarte, Michael Nicolaidis, Hakim Bederr, Yervant Zorian. 335-341 [doi]
• High-speed C-testable systolic array design for Galois-field inversionChih-Tsun Huang, Cheng-Wen Wu. 342-346 [doi]
• Efficient and accurate testing of analog-to-digital converters using oscillation-test methodKarim Arabi, Bozena Kaminska. 348-352 [doi]
• Built-in self-test methodology for A/D convertersR. de Vries, Taco Zwemstra, E. M. J. G. Bruls, Paul P. L. Regtien. 353-358 [doi]
• Reconfigurable data converter as a building block for mixed-signal testE. K. F. Lee. 359-363 [doi]
• VHDL extensions for complex transmission line simulationPeter Walker, Sumit Ghosh. 368-372 [doi]
• Acceleration of behavioral simulation on simulation specific machinesMinoru Shoji, Fumiyasu Hirose, Shintaro Shimogori, Satoshi Kowatari, Hiroshi Nagai. 373-377 [doi]
• Exploiting temporal independence in distributed preemptive circuit simulationPeter Walker, Sumit Ghosh. 378-382 [doi]
• Analogue layout generation by World Wide Web server-based agentsLes T. Walczowski, D. Nalbantis, W. A. J. Waller, Keng-Hua Shi. 384-388 [doi]
• A performance-driven placement algorithm with simultaneous Place&Route optimization for analog ICsJuan A. Prieto, Adoración Rueda, José M. Quintana, José Luis Huertas. 389-394 [doi]
• An algorithm for numerical reference generation in symbolic analysis of large analog circuitsIgnacio Garcia-Vargas, Mariano Galan, Francisco V. Fernández, Ángel Rodríguez-Vázquez. 395-399 [doi]
• Adaptive least mean square behavioral power modelingAlessandro Bogliolo, Luca Benini, Giovanni De Micheli. 404-410 [doi]
• Fast power loss calculation for digital static CMOS circuitsSergey Gavrilov, Alexey Glebov, S. Rusakov, David Blaauw, Larry G. Jones, Gopalakrishnan Vijayan. 411-415 [doi]
• Monte-Carlo approach for power estimation in sequential circuitsVikram Saxena, Farid N. Najm, Ibrahim N. Hajj. 416-420 [doi]
• Hybrid symbolic-explicit techniques for the graph coloring problemSilvia Chiusano, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda. 422-426 [doi]
• A constructive approach towards correctness of synthesis-application within retimingDirk Eisenbiegler, Ramayya Kumar, Christian Blumenröhr. 427-431 [doi]
• A symbolic core approach to the formal verification of integrated mixed-mode applicationsStefan Hendricx, Luc J. M. Claesen. 432-436 [doi]
• A novel methodology for designing TSC networks based on the parity bit codeCristiana Bolchini, Fabio Salice, Donatella Sciuto. 440-444 [doi]
• Testing scheme for IC s clocksMichele Favalli, Cecilia Metra. 445-449 [doi]
• A totally self-checking 1-out-of-3 code error indicatorAntonis M. Paschalis, Nikolaos Gaitanis, Dimitris Gizopoulos, Panagiotis Kostarakis. 450-454 [doi]
• Cone-based clustering heuristic for list-scheduling algorithmsSriram Govindarajan, Ranga Vemuri. 456-462 [doi]
• Register synthesis for speculative computationDirk Herrmann, Rolf Ernst. 463-467 [doi]
• Multidimensional periodic scheduling: a solution approachWim F. J. Verhaegh, Paul E. R. Lippens, Emile H. L. Aarts, Jef L. van Meerbergen. 468-474 [doi]
• Multi-thread graph: a system model for real-time embedded software synthesisFilip Thoen, J. Van Der Steen, G. de Jong, Gert Goossens, Hugo De Man. 476-481 [doi]
• PCC: a modeling technique for mixed control/data flow systemsThorsten Grötker, R. Schoenen, Heinrich Meyr. 482-486 [doi]
• Procedure cloning: a transformation for improved system-level functional partitioningFrank Vahid. 487-492 [doi]
• A fault diagnosis methodology for the UltraSPARC:::TM:::-I microprocessorSridhar Narayanan, R. Srinivasan, R. P. Kunda, Marc E. Levitt, Saied Bozorgui-Nesbat. 494-500 [doi]
• Improved diagnosis of realistic interconnect shortsJosé T. de Sousa, Peter Y. K. Cheung. 501-505 [doi]
• On improving genetic optimization based test generationIrith Pomeranz, Sudhakar M. Reddy. 506-511 [doi]
• Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networksLuca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi. 514-520 [doi]
• Low power FSM design using Huffman-style encodingPrasoon Surti, Liang-Fang Chao, Akhilesh Tyagi. 521-525 [doi]
• Improving the accuracy of support-set finding method for power estimation of combinational circuitsHoon Choi, Seung Ho Hwang. 526-530 [doi]
• Practical concurrent ASIC and system design and verificationI. Gibson, C. Amies. 532-536 [doi]
• A methodology for hardware architecture trade-off at different levels of abstractionC. Schneider. 537-541 [doi]
• Synthesis of multi-rate and variable rate circuits for high speed telecommunications applicationsPatrick Schaumont, Serge Vernalde, Luc Rijnders, Marc Engels, Ivo Bolsens. 542-546 [doi]
• Testability of 2-level AND/EXOR circuitsRolf Drechsler, Harry Hengster, Horst Schäfer, Joachim Hartmann, Bernd Becker. 548-553 [doi]
• On the use of reset to increase the testability of interconnected finite-state machinesIrith Pomeranz, Sudhakar M. Reddy. 554-559 [doi]
• A new approach to build a low-level malicious fault list starting from high-level description and alternative graphsAlfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Raimund Ubar. 560-565 [doi]
• On-chip analog output response compactionMichel Renovell, Florence Azaïs, Yves Bertrand. 568-572 [doi]
• A new quality estimation methodology for mixed-signal and analogue ICsThomas Olbrich, Ian A. Grout, Y. E. Aimine, Andrew M. D. Richardson, J. Contensou. 573-580 [doi]
• Compact structural test generation for analog macrosV. Kaal, Hans G. Kerkhoff. 581-587 [doi]
• Accurate high level datapath power estimationJim E. Crenshaw, Majid Sarrafzadeh. 590-596 [doi]
• Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay modelSalvador Manich, Joan Figueras. 597-602 [doi]
• Internal power modelling and minimization in CMOS invertersS. Turgis, Jean Michel Daga, J. M. Portal, Daniel Auvergne. 603-608 [doi]
• A new field programmable system-on-a-chip for mixed signal integrationJulio Faura, C. Horton, B. Krah, Joan Cabestany, M. A. Aguirre, Josep Maria Insenser. 610 [doi]
• PROPHID: a data-driven multi-processor architecture for high-performance DSPJeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess. 611 [doi]
• ReCode: the design and re-design of the instruction codes for embedded instruction-set processorsClifford Liem, Pierre G. Paulin, Ahmed Amine Jerraya. 612 [doi]
• A real-time smart sensor system for visual motion estimationT. Rowekamp, L. Peters. 613 [doi]
• Full custom chip set for high speed serial communications up to 2.48 Gbit/sJ. Gonzalez-Torres, P. A. Mateos, J. M. Hernandez. 614 [doi]
• An asynchronous architecture for digital signal processorsM. R. Karthikeyan, Soumitra Kumar Nandy. 615 [doi]
• Test synthesis for DC test of switched-capacitors circuitsHassan Ihs, Christian Dufaza. 616 [doi]
• SISSSI-A tool for dynamic electro-thermal simulation of analog VLSI cellsVladimir Székely, A. Pahi, András Poppe, Márta Rencz, A. Csendes. 617 [doi]
• Design of oscillation-based test structures for active RC filtersMarina Santo Zarnik, Franc Novak, Srecko Macek. 618 [doi]
• Using constraint logic programming in memory synthesis for general purpose computersRenate Beckmann, Jürgen Herrmann. 619 [doi]
• Optimal scheduling for fast systolic array implementationsIgor Ozimek, R. Verlic, Jurij F. Tasic. 620 [doi]
• Scheduling using mixed arithmetic: an ILP formulationAnne Mignotte, Olivier Peyran. 621 [doi]
• Performance verification using partial evaluation and interval analysisJeffrey Walrath, Ranga Vemuri, W. Bradley. 622 [doi]
• Design and verification of the sequential systems automata using temporal logic specificationsA. Ursu, G. Gruita, S. Zaporojan. 623 [doi]
• Application independent module generation in analog layoutsMarkus Wolf, Ulrich Kleine. 624 [doi]
• A scheme for multiple on-chip signature checking for embedded SRAMsMohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar. 625 [doi]
• Design of partially parallel scan chainYoshinobu Higami, Kozo Kinoshita. 626 [doi]
• March LA: a test for linked memory faultsA. J. van de Goor, Georgi Gaydadjiev, Vyacheslav N. Yarmolik, V. G. Mikitjuk. 627 [doi]
• The input pattern fault model and its applicationRonald D. Blanton, John P. Hayes. 628 [doi]
• A monolithic off-chip IDDQ monitorM. Svajda, B. Straka, Hans A. R. Manhaeve. 629 [doi]
• Extension of the boundary-scan architecture and new idea of BIST for more effective testing and self-testing of interconnectionsAdam Kristof. 630 [doi]