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Viewing Publication 1 - 53 from 53

2006

Statistical Timing for Parametric Yield Prediction of Digital Integrated CircuitsJochen A. G. Jess, K. Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah. tcad, 25(11):2376-2392, 2006. [doi]

2003

Statistical timing for parametric yield prediction of digital integrated circuitsJochen A. G. Jess, K. Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah. dac 2003: 932-937 [doi]

Codeübersetzung unter Zeitvorgaben für eingebettete SignalprozessorenJochen A. G. Jess. it, 45(6):327-335, 2003. [doi]

2002

Parametric Yield Estimation for Deep Sub- Micron VLSI CircuitsJochen A. G. Jess. sbcci 2002: 387 [doi]

2001

2000

A code-motion pruning technique for global schedulingLuiz C. V. dos Santos, Marc J. M. Heijligers, C. A. J. van Eijk, J. Van Eijnhoven, Jochen A. G. Jess. todaes, 5(1):1-38, 2000. [doi]

Constraint analysis for code generation: basic techniques and applications in FACTSKoen Van Eijk, Bart Mesman, Carlos A. Alba Pinto, Qin Zhao, Marco Bekooij, Jef L. van Meerbergen, Jochen A. G. Jess. todaes, 5(4):774-793, 2000. [doi]

Designing electronic engines with electronic engines: 40 years ofbootstrapping of a technology upon itselfJochen A. G. Jess. tcad, 19(12):1404-1427, 2000. [doi]

Prophid: A Platform-Based Design MethodJeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess. dafes, 6(1):5-37, 2000. [doi]

Address Satisfaction for Storage Files with Fifos or Stacks during Scheduling of DSP AlgorithmsCarlos A. Alba Pinto, Koen Van Eijk, Bart Mesman, Jochen A. G. Jess. sbcci 2000: 107-112 [doi]

Register Binding for Predicated Execution in DSP ApplicationsQin Zhao, C. A. J. van Eijk, Carlos A. Alba Pinto, Jochen A. G. Jess. sbcci 2000: 113-118 [doi]

1999

A Reordering Technique for Efficient Code MotionLuiz C. V. dos Santos, Jochen A. G. Jess. dac 1999: 296-299 [doi]

Exploiting State Equivalence on the Fly while Applying Code Motion and SpeculationLuiz C. V. dos Santos, Jochen A. G. Jess. date 1999: 609 [doi]

Constraint analysis for DSP code generationBart Mesman, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess. tcad, 18(1):44-57, 1999. [doi]

1998

Stream Communication between Real-Time Tasks in a High-Performance MultiprocessorJeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess. date 1998: 125-131 [doi]

A Constraint Driven Approach to Loop Pipelining and Register BindingBart Mesman, Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess. date 1998: 377-383 [doi]

1997

1996

1995

Run-time consistency checking in discrete simulation modelsJ. W. G. Fleurkens, C. A. J. van Eijk, Jochen A. G. Jess. date 1995: 223-227 [doi]

High-level synthesis scheduling and allocation using genetic algorithmsMarc J. M. Heijligers, L. J. M. Cluitmans, Jochen A. G. Jess. aspdac 1995: [doi]

Analysis and reduction of glitches in synchronous networksJeroen A. J. Leijten, Jef L. van Meerbergen, Jochen A. G. Jess. date 1995: 398-403 [doi]

Efficient code generation for in-house DSP-coresMarino T. J. Strik, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess, Stefaan Note. date 1995: 244-251 [doi]

Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP CoresAdwin H. Timmer, Marino T. J. Strik, Jef L. van Meerbergen, Jochen A. G. Jess. dac 1995: 593-598 [doi]

Exact scheduling strategies based on bipartite graph matchingAdwin H. Timmer, Jochen A. G. Jess. date 1995: 42-47 [doi]

1994

1993

On Accurate Modeling and Efficient Simulation of CMOS OpensChennian Di, Jochen A. G. Jess. itc 1993: 875-882

On CMOS bridge fault modeling and test pattern evaluationChennian Di, Jochen A. G. Jess. vts 1993: 116-119 [doi]

A Multiple Terminal Net Routing Algorithm Using Failure PredictionEd P. Huijbregts, Jochen A. G. Jess. vlsid 1993: 84-89

General gate array routing using a k-terminal net routing algorithm with failure predictionEd P. Huijbregts, Jochen A. G. Jess. tvlsi, 1(4):473-481, 1993. [doi]

Execution interval analysis under resource constraintsAdwin H. Timmer, Jochen A. G. Jess. iccad 1993: 454-459 [doi]

Parameter Monitoring: Advantages and PitfallsM. M. A. van Rosmalen, Keith Baker, Eric Bruls, Jochen A. G. Jess. itc 1993: 115-124

Fast Multi-Layer Critical Area ComputationHua Xue, Chennian Di, Jochen A. G. Jess. dft 1993: 117-124

A net-oriented method for realistic fault analysisHua Xue, Chennian Di, Jochen A. G. Jess. iccad 1993: 78-83 [doi]

1992

Foreground memory management in data path synthesisLeon Stok, Jochen A. G. Jess. ijcta, 20(3):235-255, 1992. [doi]

1991

A Generic Method to Develop a Defect Monitoring System for IC ProcessesEric Bruls, F. Camerik, H. J. Kretschman, Jochen A. G. Jess. itc 1991: 218-227

1990

Gate sizing in MOS digital circuits with linear programmingMichel R. C. M. Berkelaar, Jochen A. G. Jess. eurodac 1990: 217-221 [doi]

1989

Qualification and Quantification of Process-Induced Product-Related DefectsF. Camerik, P. A. J. Dirks, Jochen A. G. Jess. itc 1989: 643-652

On the design and implementation of a wafer yield editorJosé Pineda de Gyvez, Jochen A. G. Jess. tcad, 8(8):920-925, 1989. [doi]

A layout defect-sensitivity extractorJosé Pineda de Gyvez, Jochen A. G. Jess. iccad 1989: 538-541 [doi]

1988

Technology mapping for standard-cell generatorsMichel R. C. M. Berkelaar, Jochen A. G. Jess. iccad 1988: 470-473 [doi]

1982

A Data Structure for Parallel ::::L/U:::: DecompositionJochen A. G. Jess, H. G. M. Kees. TC, 31(3):231-239, 1982.

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Publications by 'Jochen A. G. Jess'

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2006

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