Table of Contents

• Software Scheduling in the Co-Synthesis of Reactive Real-Time SystemsPai H. Chou, Gaetano Borriello. 1-4 [doi]
• Synthesis of Instruction Sets for Pipelined MicroprocessorsIng-Jer Huang, Alvin M. Despain. 5-11 [doi]
• A Methodology for Efficient Estimation of Switching Activity in Sequential Logic CircuitsJosé C. Monteiro, Srinivas Devadas, Bill Lin. 12-17 [doi]
• ASTRX/OBLX: Tools for Rapid Synthesis of High-Performance Analog CircuitsEmil S. Ochotta, Rob A. Rutenbar, L. Richard Carley. 24-30 [doi]
• Simultaneous Placement and Module Optimization of Analog IC sEdoardo Charbon, Enrico Malavasi, Davide Pandini, Alberto L. Sangiovanni-Vincentelli. 31-35 [doi]
• Stochastic Optimization Approach to Transistor Sizing for CMOS VLSI CircuitsSharad Mehrotra, Paul D. Franzon, Wentai Liu. 36-40 [doi]
• Executive Perspective and Vision of the Future of EDA (Panel)Joseph B. Costello, Walden C. Rhines, Aart J. de Geus, Alain Hanover, Doug Fairbairn, Rick Carlson, Ronald Collett. 48 [doi]
• A Communicating Petri Net Model for the Design of Concurrent Asynchronous ModulesGjalt G. de Jong, Bill Lin. 49-55 [doi]
• Basic Gate Implementation of Speed-Independent CircuitsAlex Kondratyev, Michael Kishinevsky, Bill Lin, Peter Vanbekbergen, Alexandre Yakovlev. 56-62 [doi]
• A Modular Partitioning Approach for Asynchronous Circuit SynthesisRuchir Puri, Jun Gu. 63-69 [doi]
• Performance Analysis Based on Timing SimulationChristian D. Nielsen, Michael Kishinevsky. 70-76 [doi]
• Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other ApplicationsPranav Ashar, Sharad Malik. 77-80 [doi]
• An Exact Algorithm for Selecting Partial Scan Flip-FlopsSrimat T. Chakradhar, Arun Balakrishnan, Vishwani D. Agrawal. 81-86 [doi]
• Resynthesis and Retiming for Optimum Partial ScanSrimat T. Chakradhar, Sujit Dey. 87-93 [doi]
• Clock Grouping: A Low Cost DFT Methodology for Delay TestingWen-Chang Fang, Sandeep K. Gupta. 94-99 [doi]
• Exact Minimum Cycle Times for Finite State MachinesWilliam K. C. Lam, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 100-105 [doi]
• Interface Timing Verification with Application to SynthesisElizabeth A. Walkup, Gaetano Borriello. 106-112 [doi]
• Automated Multi-Cycle Symbolic Timing Verification of Microprocessor-Based DesignsAnurag P. Gupta, Daniel P. Siewiorek. 113-119 [doi]
• The Minimization and Decomposition of Interface State MachinesAjay J. Daga, William P. Birmingham. 120-125 [doi]
• Statistical Delay Modeling in Logic Design and SynthesisHorng-Fei Jyu, Sharad Malik. 126-130 [doi]
• Partnering with EDA Vendors: Tips, Techniques, and the Role of StandardsSean Murphy. 131-134 [doi]
• Cost of Silicon Viewed from VLSI Design PerspectiveWojciech Maly. 135-142 [doi]
• Memory Estimation for High Level SynthesisIngrid Verbauwhede, Chris J. Scheers, Jan M. Rabaey. 143-148 [doi]
• Minimization of Memory Traffic in High-Level SynthesisDavid J. Kolson, Alexandru Nicolau, Nikil D. Dutt. 149-154 [doi]
• Sequencer-Based Data Path Synthesis of Regular Iterative AlgorithmsMohammed Aloqeely, C. Y. Roger Chen. 155-160 [doi]
• Intellectual Property Protection in the EDA IndustryDennis S. Fernandez. 161-163 [doi]
• Software Patents and Their Potential Impact on the EDA Community (Panel)William M. van Cleemput, Ewald Detjens, Herman Beke, George C. Chen, Joseph Hustein, William Lattin, Dennis S. Fernandez. 164 [doi]
• Switch Bound Allocation for Maximizing Routability in Timing-Driven Routing of FPGAsKai Zhu, D. F. Wong. 165-170 [doi]
• Routing in a New 2-Dimensional FPGA/FPIC Routing ArchitectureYachyang Sun, C. L. Liu. 171-176 [doi]
• A Global Router Optimizing Timing and Area for High-Speed Bipolar LSI sIkuo Harada, Hitoshi Kitazawa. 177-181 [doi]
• A Unified Approach to Multilayer Over-the-Cell RoutingSreekrishna Madhwapathy, Naveed A. Sherwani, Siddharth Bhingarde, Anand Panyam. 182-187 [doi]
• PESDA and Design Abstraction: How High is Up? (Panel)Geoffrey Bunza, Steve Schulz, Tommy Jansson, Alex Silbey, Steve Ma, Edward H. Frank. 188 [doi]
• Efficient Substitution of Multiple Constant Multiplications by Shifts and Additions Using Iterative Pairwise MatchingMiodrag Potkonjak, Mani B. Srivastava, Anantha Chandrakasan. 189-194 [doi]
• Clock Period Optimization During Resource Sharing and AssignmentSubhrajit Bhattacharya, Sujit Dey, Franc Brglez. 195-200 [doi]
• Optimizing Resource Utilization and Testability Using Hot Potato TechniquesMiodrag Potkonjak, Sujit Dey. 201-205 [doi]
• Microarchitectural Synthesis of VLSI Designs with High Test ConcurrencyIan G. Harris, Alex Orailoglu. 206-211 [doi]
• Rectification of Multiple Logic Design Errors in Multiple Output CircuitsMasahiro Tomita, Tamotsu Yamamoto, Fuminori Sumikawa, Kotaro Hirano. 212-217 [doi]
• Error Diagnosis for Transistor-Level VerificationAndreas Kuehlmann, David Ihsin Cheng, Arvind Srinivasan, David P. LaPotin. 218-224 [doi]
• Heuristic Minimization of BDDs Using Don t CaresThomas R. Shiple, Ramin Hojati, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton. 225-231 [doi]
• Clock Skew Minimization During FPGA PlacementKai Zhu, D. F. Wong. 232-237 [doi]
• Multi-way Netlist Partitioning into Heterogeneous FPGAs and Minimization of Total Device Cost and InterconnectRoman Kuznar, Franc Brglez, Baldomir Zajc. 238-243 [doi]
• Circuit Partitioning for Huge Logic Emulation SystemsNan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof. 244-249 [doi]
• Experience with Image Compression Chip Design using Unified System Construction ToolsPravil Gupta, Chih-Tung Chen, J. C. DeSouza-Batista, Alice C. Parker. 250-256 [doi]
• The Use of CAD Frameworks in a CIM EnvironmentWang Tek Kee, Dennis Sng, Jacob Gan, Low Kin Kiong. 257-261 [doi]
• Basic Concept of Cooperative Timing-driven Design Automation Technology for High-speed RISC Processor HARP-1Hidekazu Terai, Kazutoshi Gemma, Yohsuke Nagao, Yasuo Satoh, Yasuhiro Ohno. 262-269 [doi]
• Probabilistic Analysis of Large Finite State MachinesGary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi. 270-275 [doi]
• New Techniques for Efficient Verification with Implicitly Conjoined BDDsAlan J. Hu, Gary York, David L. Dill. 276-282 [doi]
• BDD Variable Ordering for Interacting Finite State MachinesAdnan Aziz, Serdar Tasiran, Robert K. Brayton. 283-288 [doi]
• Auxiliary Variables for Extending Symbolic Traversal Techniques to Data PathsGianpiero Cabodi, Paolo Camurati, Stefano Quer. 289-293 [doi]
• Microprocessor Testing: Which Technique is Best? (Panel)Jacob A. Abraham, Sandip Kundu, Janak H. Patel, Manuel A. d Abreu, Bulent I. Dervisoglu, Marc E. Levitt, Hector R. Sucar, Ron G. Walther. 294 [doi]
• Placement and Routing for a Field Programmable Multi-Chip ModuleSanko Lan, Avi Ziv, Abbas El Gamal. 295-300 [doi]
• Performance-Driven Simultaneous Place and Route for Row-Based FPGAsSudip Nag, Rob A. Rutenbar. 301-307 [doi]
• Layout Driven Logic Synthesis for FPGAsShih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska. 308-313 [doi]
• Fitting Formal Methods into the Design CycleKenneth L. McMillan. 314-319 [doi]
• Panel: Complex System Verification: The Challenge AheadRonald Collett, Mike Gianfagna, Michel Courtoy, Martin Baynes, Johan Van Ginderdeuren, Kenneth L. McMillan, Stephen Ricca, Alberto L. Sangiovanni-Vincentelli, Steve Sapiro, Naeem Zafar. 320 [doi]
• A Comprehensive Approach to Logic Synthesis and Physical Design for Two-Dimensional Logic ArraysAndisheh Sarabi, Ning Song, Malgorzata Chrzanowska-Jeske, Marek A. Perkowski. 321-326 [doi]
• A Methodology and Algorithms for Post-Placement Delay OptimizationLalgudi N. Kannan, Peter Suaris, Hong-Gee Fang. 327-332 [doi]
• Technology Mapping Using Fuzzy LogicSasan Iman, Massoud Pedram, Kamal Chaudhary. 333-338 [doi]
• Boolean Matching Using Generalized Reed-Muller FormsChien-Chung Tsai, Malgorzata Marek-Sadowska. 339-344 [doi]
• Extraction of a High-level structural Representation from Circuit Descriptions with Applications to DFT/BISTIshwar Parulkar, Melvin A. Breuer, Charles Njinda. 345-356 [doi]
• DFBT: A Design-for-Testability Method Based on Balance TestingKrishnendu Chakrabarty, John P. Hayes. 351-357 [doi]
• Design-for-Testability for Path Delay Faults in Large Combinatorial Circuits Using Test-PointsIrith Pomeranz, Sudhakar M. Reddy. 358-364 [doi]
• Generation of High Quality Non-Robust Tests for Path Delay FaultsKwang-Ting Cheng, Hsi-Chuan Chen. 365-369 [doi]
• On Testing Wave Pipelined CircuitsJui-Ching Shyur, Hung-Pin Chen, Tai-Ming Parng. 370-374 [doi]
• An Efficient Zero-Skew Routing AlgorithmMasato Edahiro. 375-380 [doi]
• Rectilinear Steiner Trees with Minimum Elmore DelayKenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins. 381-386 [doi]
• Minimal Delay Interconnect Design Using Alphabetic TreesAshok Vittal, Malgorzata Marek-Sadowska. 392-396 [doi]
• Algorithmic Aspects of Three Dimensional MCM RoutingQiong Yu, Sandeep Badida, Naveed A. Sherwani. 397-401 [doi]
• Routing for ManufacturabilityHua Xue, Ed P. Huijbregts, Jochen A. G. Jess. 402-406 [doi]
• Technology Summit - A View from the Top (Panel)Andrew J. Graham, Richard Goldman, Wen-Tsuen Chen, Kerry Hanson, Nikolay G. Malishev, Shin-ichi Nakayama. 407 [doi]
• Optimum Functional Decomposition Using EncodingRajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 408-414 [doi]
• Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision DiagramsRolf Drechsler, Andisheh Sarabi, Michael Theobald, Bernd Becker, Marek A. Perkowski. 415-419 [doi]
• Calculation of Unate Cube Set Algebra Using Zero-Suppressed BDDsShin-ichi Minato. 420-424 [doi]
• Performance Optimization Using Exact SensitizationAlexander Saldanha, Heather Harkness, Patrick C. McGeer, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 425-429 [doi]
• Random Generation of Test Instances for Logic OptimizersKazuo Iwama, Kensuke Hino. 430-434 [doi]
• Hardware-Software Co-Design and ESDAKurt Keutzer. 435-436 [doi]
• Manifestations of Heterogeneity in Hardware/Software Co-DesignAsawaree Kalavade, Edward A. Lee. 437-438 [doi]
• Hardware/Software Co-SimulationJames A. Rowson. 439-440 [doi]
• A System for Incremental Synthesis to Gate-Level and Reoptimization Following RTL Design ChangesS. C. Prasad, P. Anirudhan, Patrick W. Bosshart. 441-446 [doi]
• Lessons in Language Design: Cost/Benefit analysis of VHDL FeaturesOz Levia, Serge Maginot, Jacques Rouillard. 447-453 [doi]
• HSIS: A BDD-Based Environment for Formal VerificationAdnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 454-459 [doi]
• Rapid Prototyping of ASIC Based SystemsP. H. Kelly, Kevin J. Page, Paul M. Chau. 460-465 [doi]
• Structured Design Methodology for High-Level DesignPolen Kission, Hong Ding, Ahmed Amine Jerraya. 466-471 [doi]
• Design Methodology Management Using Graph GrammarsReid A. Baldwin, Moon-Jung Chung. 472-478 [doi]
• Incorporating Speculative Execution in Exact Control-Dependent SchedulingIvan P. Radivojevic, Forrest Brewer. 479-484 [doi]
• Loop Pipelining for Scheduling Multi-Dimensional Systems via RotationNelson L. Passos, Edwin Hsing-Mean Sha, Steven C. Bass. 485-490 [doi]
• Chain Closure: A Problem in Molecular CADMaria Domenica Di Benedetto, Pasquale Lucibello, Alberto L. Sangiovanni-Vincentelli, K. Yamaguchi. 497-502 [doi]
• DA Algorithms in Non-EDA Applications: How Universal Are Our Techniques? (Panel)Patrick C. McGeer, Steven Trimberger, Erik Carlson, Dave Hightower, Ulrich Lauther, Alberto L. Sangiovanni-Vincentelli. 503 [doi]
• On Improving Fault Diagnosis for Synchronous Sequential CircuitsIrith Pomeranz, Sudhakar M. Reddy. 504-509 [doi]
• VFSIM: Vectorized Fault Simulator Using a Reduction Technique Excluding Temporarily Unobservable FaultsTakaharu Nagumo, Masahiko Nagai, Takao Nishida, Masayuki Miyoshi, Shunsuke Miyamoto. 510-515 [doi]
• An Efficient Path Delay Fault Coverage EstimatorKeerthi Heragu, Michael L. Bushnell, Vishwani D. Agrawal. 516-521 [doi]
• Path Hashing to Accelerate Delay Fault SimulationManfred Henftling, Hannes C. Wittmann, Kurt Antreich. 522-526 [doi]
• MIST - A Design Aid for Programmable Pipelined ProcessorsAlbert E. Casavant. 532-536 [doi]
• Automatic Synthesis of Pipeline Structures with Variable Data Initiation IntervalsHong Shin Jun, Sun Young Hwang. 537-541 [doi]
• Global Scheduling for High-Level Synthesis ApplicationsYaw Fann, Minjoong Rim, Rajiv Jain. 542-546 [doi]
• Protocol Generation for Communication ChannelsSanjiv Narayan, Daniel Gajski. 547-551 [doi]
• Area-Efficient Fault Detection During Self-Recovering Microarchitecture SynthesisRamesh Karri, Alex Orailoglu. 552-556 [doi]
• The Attributed-Behavior Abstraction and Synthesis ToolsLawrence F. Arnstein, Donald E. Thomas. 557-561 [doi]
• Design Reuse: Fact or Fiction? (Panel)Nikil D. Dutt, David Agnew, Raul Camposano, Antun Domic, Manfred Wiesel, Hiroto Yasuura. 562 [doi]
• Delay Analysis of VLSI Interconnections Using the Diffusion Equation ModelAndrew B. Kahng, Sudhakar Muddu. 563-569 [doi]
• MONSTR: A Complete Thermal Simulator of Electronic SystemsVladimir Koval, Igor W. Farmaga, Andrzej J. Strojwas, Stephen W. Director. 570-575 [doi]
• A Gate-Delay Model for high-Speed CMOS CircuitsFlorentin Dartu, Noel Menezes, Jessica Qian, Lawrence T. Pillage. 576-580 [doi]
• Transient Sensitivity Computation of MOSFET Circuits Using Iterated Timing Analysis and Selective-Tracing Waveform EelaxationChung-Jung Chen, Wu-Shiung Feng. 581-585 [doi]
• Hitachi-PA/50, SH Series MicrocontrollerTadahiko Nishimukai. 592-593 [doi]
• Low Power CMOS Design StrategiesMatthias Schöbinger, Tobias G. Noll. 594-595 [doi]
• Formally Verifying a Microprocessor Using a Simulation MethodologyDerek L. Beatty, Randal E. Bryant. 596-602 [doi]
• Automatic Verification of Pipelined MicroprocessorsVishal Bhagwati, Srinivas Devadas. 603-608 [doi]
• A Time Abstraction Method for Efficient Verification of Communicating SystemsEric Verlind, Tilman Kolks, Gjalt G. de Jong, Bill Lin, Hugo De Man. 609-614 [doi]
• On the Computation of the Set of Reachable States of Hybrid ModelsA. S. Krishnakumar, Kwang-Ting Cheng. 615-621 [doi]
• Efficient Simulation of Lossy and Dispersive Transmission LinesTuyen V. Nguyen. 622-627 [doi]
• A New Time-Domain Macromodel for Transient Simulation of Uniform/Nonuniform Multiconductor Transmission-Line InterconnectionsMonjurul Haque, Ali El-Zein, Salim Chowdhury. 628-633 [doi]
• An Efficient Approach to Transmission Line Simulation Using Measured or Tabulated S-parameter DataLuis Miguel Silveira, Ibrahim M. Elfadel, Jacob White, Moni Chilukuri, Kenneth S. Kundert. 634-639 [doi]
• OTTER: Optimal Termination of Transmission Lines Excluding RadiationRohini Gupta, Lawrence T. Pillage. 640-645 [doi]
• Partitioning Very Large Circuits Using Analytical Placement TechniquesBernhard M. Riess, Konrad Doll, Frank M. Johannes. 646-651 [doi]
• Multi-Way Partitioning Via Spacefilling curves and Dynamic ProgrammingCharles J. Alpert, Andrew B. Kahng. 652-657 [doi]
• Data Flow Partitioning for Clock Period and Latency MinimizationLung-Tien Liu, Minshine Shih, Chung-Kuan Cheng. 658-663 [doi]
• A Fast and Stable Hybrid Genetic Algorithm for the Ratio-Cut Partitioning Problem on HypergraphsThang Nguyen Bui, Byung Ro Moon. 664-669 [doi]
• Acyclic Multi-Way Partitioning of Boolean NetworksJason Cong, Zheng Li, Rajive Bagrodia. 670-675 [doi]
• Design Automation Tools for FPGA Design (Panel)Kella Knack, Gordan Hyland, Jim Jasmin, John Frediani, Tom Reiner, Steven Trimberger, Gabriele Saucier. 676 [doi]
• A Fully Implicit Algorithm for Exact State MinimizationTimothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 684-690 [doi]
• Sequential Circuit Test Generation in a Genetic Algorithm FrameworkElizabeth M. Rudnick, Janak H. Patel, Gary S. Greenstein, Thomas M. Niermann. 698-704 [doi]
• Dynamic Search-Space Pruning Techniques in Path SensitizationJoão P. Marques Silva, Karem A. Sakallah. 705-711 [doi]
• Functional Test Generation for FSMs by Fault ExtractionBapiraju Vinnakota, Jason Andrews. 712-715 [doi]
• ProperHITEC: A Portable, Parallel, Object-Oriented Approach to Sequential Test GenerationSteven Parkes, Prithviraj Banerjee, Janak H. Patel. 717-721 [doi]
• Modeling of Intermediate Node States in switch-Level NetworksPeter Dahlgren, Peter Lidén. 722-727 [doi]
• Statistical Estimation of the Switching Activity in Digital CircuitsMichael G. Xakellis, Farid N. Najm. 728-733 [doi]
• Improving the Accuracy of Circuit Activity MeasurementBhanu Kapoor. 734-739 [doi]