Nan-Chi Chou - researchr alias

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Viewing Publication 1 - 18 from 18

2011

Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip CommunicationsRenshen Wang, Yulei Zhang, Nan-Chi Chou, Evangeline F. Y. Young, Chung-Kuan Cheng, Ronald L. Graham. tcad, 30(2):167-179, 2011. [doi]

2009

Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communicationsRenshen Wang, Nan-Chi Chou, Bill Salefski, Chung-Kuan Cheng. dac 2009: 166-171 [doi]

2007

Efficient Timing Analysis With Known False Paths Using Biclique CoveringShuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Michael Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris, Chung-Kuan Cheng. tcad, 26(5):959-969, 2007. [doi]

2005

2004

Fast adders in modern FPGAsJianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris. fpga 2004: 250 [doi]

Incremental physical resynthesis for timing optimizationPeter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou. fpga 2004: 99-108 [doi]

2003

1995

Local ratio cut and set covering partitioning for huge logic emulation systemsNan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof. tcad, 14(9):1085-1092, 1995. [doi]

On general zero-skew clock net constructionNan-Chi Chou, Chung-Kuan Cheng. tvlsi, 3(1):141-146, 1995. [doi]

1994

Circuit Partitioning for Huge Logic Emulation SystemsNan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof. dac 1994: 244-249 [doi]

A multi-probe approach for MCM substrate testingSo-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu. tcad, 13(1):110-121, 1994. [doi]

1993

Performance-driven partitioning using retiming and replicationLung-Tien Liu, Minshine Shih, Nan-Chi Chou, Chung-Kuan Cheng, Walter H. Ku. iccad 1993: 296-299 [doi]

1992

An optimal probe testing algorthm for the connectivity verification of MCM substratesSo-Zen Yao, Nan-Chi Chou, Chung-Kuan Cheng, T. C. Hu. iccad 1992: 264-267 [doi]

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