Table of Contents

• Architectures and algorithms for synthesizable embedded programmable logic coresNoha Kafafi, Kimberly Bozman, Steven J. E. Wilton. 3-11 [doi]
• The Stratix:::TM::: routing and logic architectureDavid M. Lewis, Vaughn Betz, David Jefferson, Andy Lee, Christopher Lane, Paul Leventis, Sandy Marquardt, Cameron McClintock, Bruce Pedersen, Giles Powell, Srinivas Reddy, Chris Wysocki, Richard Cliff, Jonathan Rose. 12-20 [doi]
• Hardware-assisted simulated annealing with application for fast FPGA placementMichael G. Wrighton, André DeHon. 33-42 [doi]
• Parallel placement for field-programmable gate arraysPak K. Chan, Martine D. F. Schlag. 43-50 [doi]
• I/O placement for FPGAs with multiple I/O standardsWai-Kei Mak. 51-57 [doi]
• Wire type assignment for FPGA routingSeokjin Lee, Hua Xiang, D. F. Wong, Richard Y. Sun. 61-67 [doi]
• PipeRoute: a pipelining-aware router for FPGAsAkshay Sharma, Carl Ebeling, Scott Hauck. 68-77 [doi]
• Stochastic, spatial routing for hypergraphs, trees, and meshesRandy Huang, John Wawrzynek, André DeHon. 78-87 [doi]
• Implementation of BEE: a real-time large-scale hardware emulation engineChen Chang, Kimmo Kuusilinna, Brian C. Richards, Robert W. Brodersen. 91-99 [doi]
• High-level modeling and FPGA prototyping of microprocessorsJoydeep Ray, James C. Hoe. 100-107 [doi]
• Reducing pin and area overhead in fault-tolerant FPGA-based designsFernanda Lima, Luigi Carro, Ricardo Augusto da Luz Reis. 108-117 [doi]
• A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technologyJong-Ru Guo, Chao You, Kuan Zhou, Bryan S. Goda, Russell P. Kraft, John F. McDonald. 145-153 [doi]
• Design of FPGA interconnect for multilevel metalizationRaphael Rubin, André DeHon. 154-163 [doi]
• Automatic transistor and physical design of FPGA tiles from an architectural specificationKetan Padalia, Ryan Fung, Mark Bourgeault, Aaron Egier, Jonathan Rose. 164-172 [doi]
• Architecture evaluation for power-efficient FPGAsFei Li, Deming Chen, Lei He, Jason Cong. 175-184 [doi]
• An FPGA architecture with enhanced datapath functionalityKatarzyna Leijten-Nowak, Jef L. van Meerbergen. 195-204 [doi]
• A fully pipelined memoryless 17.8 Gbps AES-128 encryptorKimmo U. Järvinen, Matti Tommiska, Jorma Skyttä. 207-215 [doi]
• A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES RIJNDAELFrançois-Xavier Standaert, Gaël Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat. 216-224 [doi]
• Energy-efficient signal processing using FPGAsSeonil Choi, Ronald Scrofano, Viktor K. Prasanna, Ju-wook Jang. 225-234 [doi]
• FPGA-based design of an evolutionary controller for collision-free robot navigationM. A. Hannan Bin Azhar, Keith R. Dimond. 237 [doi]
• FPGA implementation of a fast Hadamard transformer for WCDMASanat Kamal Bahl, Jim Plusquellic. 237 [doi]
• Making area-performance tradeoffs at the high level using the AccelFPGA compiler for FPGAsPrithviraj Banerjee, Vikram Saxena, J. R. Uribe, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, R. Anderson. 237 [doi]
• Design framework for the implementation of the 2-D orthogonal discrete wavelet transform on FPGAAbdsamad Benkrid, Danny Crookes, Khaled Benkrid. 238 [doi]
• A logic based approach to hardware abstractionKhaled Benkrid, S. Belkacemi, Danny Crookes. 238 [doi]
• A single-FPGA implementation of image connected component labellingKhaled Benkrid, S. Sukhsawas, Danny Crookes, S. Belkacemi. 238 [doi]
• An estimation and exploration methodology from system-level specifications: application to FPGAsSebastien Bilavarn, Guy Gogniat, Jean Luc Philippe. 239 [doi]
• A granularity-based classification model for systems-on-a-chipStephan Bingemer, Peter Zipf, Manfred Glesner. 239 [doi]
• Design of a fingerprint system using a hardware/software environmentVanderlei Bonato, Rolf Fredi Molz, João Carlos Furtado, Marcos Flôres Ferrão, Fernando Gehm Moraes. 240 [doi]
• Customized regular channel design in FPGAsElaheh Bozorgzadeh, Majid Sarrafzadeh. 240 [doi]
• Track placement: orchestrating routing structures to maximize routabilityKatherine Compton, Scott Hauck. 241 [doi]
• Implementation of digital fixed-point approximations to continuous-time IIR filtersJoan Carletta, Robert J. Veillette, Frederick W. Krach, Zhengwei Fang. 241 [doi]
• On hiding latency in reconfigurable systems: the case of merge-sort for an FPGA-based systemHossam A. ElGindy, George Ferizis. 242 [doi]
• Recursive circuit clustering for minimum delay and areaMehrdad Eslami Dehkordi, Stephen Dean Brown. 242 [doi]
• Using FPGAs for data and reorganization engines: preliminary results for spatial pointer-based data structuresPedro C. Diniz, Joonseok Park. 242 [doi]
• On computation and resource management in an FPGA-based computation environmentSoheil Ghiasi, Karlene Nguyen, Elaheh Bozorgzadeh, Majid Sarrafzadeh. 243 [doi]
• A SC-based novel configurable analog cellBinlin Guo, Jiarong Tong. 243 [doi]
• FPGAs in critical hardware/software systemsAdrian J. Hilton, Gemma Townson, Jon G. Hall. 244 [doi]
• An automated and power-aware framework for utilization of IP cores in hardware generated from C descriptions targeting FPGAsAlex K. Jones, Prithviraj Banerjee. 244 [doi]
• Power-aware architectures and circuits for FPGA-based signal processingFrank Honoré, Benton H. Calhoun, Anantha Chandrakasan. 244 [doi]
• Reconfigurable randomized K-way graph partitioningFatih Kocan. 245 [doi]
• Synthetic circuit generation using clustering and iterationPaul D. Kundarewich, Jonathan Rose. 245 [doi]
• An FPGA architecture with built-in error correction capabilityParag K. Lala, B. Kiran Kumar. 245 [doi]
• Wireless sensor networks: a power-scalable motion estimation IP for hybrid video codingFederico Quaglio, Maurizio Martina, Fabrizio Vacca, Guido Masera, Andrea Molino, Gianluca Piccinini, Maurizio Zamboni. 246 [doi]
• Lattice adaptive filter implementation for FPGAZdenek Pohl, Rudolf Matousek, Jiri Kadlec, Milan Tichý, Miroslav Lícko. 246 [doi]
• A physical retiming algorithm for field programmable gate arraysPeter Suaris, Dongsheng Wang, Pei-Ning Guo, Nan-Chi Chou. 247 [doi]
• Design strategies and modified descriptions to optimize cipher FPGA implementations: fast and compact results for DES and triple-DESGaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat. 247 [doi]
• Application-dependent testing of FPGAs for bridging faultsMehdi Baradaran Tahoori. 248 [doi]
• A high resolution diagnosis technique for open and short defects in FPGA interconnectsMehdi Baradaran Tahoori. 248 [doi]
• A four-bit full adder implemented on fast SiGe FPGAs with novel power control schemeKuan Zhou, Michael Chu, Chao You, Jong-Ru Guo, Channakeshav, John Mayega, John F. McDonald, Russell P. Kraft, Bryan S. Goda. 248 [doi]