Gianluca Piccinini - researchr alias

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Viewing Publication 1 - 53 from 53

2023

2021

A Reconfigurable Field-Coupled Nanocomputing Paradigm on Uniform Molecular MonolayersYuri Ardesi, Giuliana Beretta, Christian Fabiano, Mariagrazia Graziano, Gianluca Piccinini. icrc 2021: 124-128 [doi]

SCERPA Simulation of Clocked Molecular Field-Coupling NanocomputingYuri Ardesi, Giovanna Turvani, Mariagrazia Graziano, Gianluca Piccinini. tvlsi, 29(3):558-567, 2021. [doi]

2020

SCERPA: A Self-Consistent Algorithm for the Evaluation of the Information Propagation in Molecular Field-Coupled NanocomputingYuri Ardesi, Ruiyu Wang, Giovanna Turvani, Gianluca Piccinini, Mariagrazia Graziano. tcad, 39(10):2749-2760, 2020. [doi]

2019

Bistable Propagation of Monostable Molecules in Molecular Field-Coupled NanocomputingYuri Ardesi, Luca Gnoli, Mariagrazia Graziano, Gianluca Piccinini. prime 2019: 225-228 [doi]

2018

Nanoarrays for Systolic Biosequence AnalysisMalik Ashter Mehdy, Aleandro Antidormi, Mariagrazia Graziano, Gianluca Piccinini. jcsc, 27(12):1-26, 2018. [doi]

2015

Process Variability and Electrostatic Analysis of Molecular QCAMariagrazia Graziano, Azzurra Pulimeno, Ruiyu Wang, Xiang Wei, Massimo Ruo Roch, Gianluca Piccinini. jetc, 12(2):18, 2015. [doi]

Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWTMaurizio Martina, Guido Masera, Massimo Ruo Roch, Gianluca Piccinini. tcas, 62-I(8):2103-2113, 2015. [doi]

2014

Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-AdvancedCarlo Condo, Maurizio Martina, Gianluca Piccinini, Guido Masera. spl, 21(11):1380-1384, 2014. [doi]

Understanding a Bisferrocene Molecular QCA WireAzzurra Pulimeno, Mariagrazia Graziano, Aleandro Antidormi, Ruiyu Wang, Ali Zahir, Gianluca Piccinini. In Neal G. Anderson, Sanjukta Bhanja, editors, Field-Coupled Nanocomputing - Paradigms, Progress, and Perspectives. Volume 8280 of Lecture Notes in Computer Science, pages 307-338, Springer, 2014. [doi]

A Parallel Radix-Sort-Based VLSI Architecture for Finding the First W Maximum/Minimum ValuesGuoping Xiao, Maurizio Martina, Guido Masera, Gianluca Piccinini. tcas, 61-II(11):890-894, 2014. [doi]

Molecular transistor circuits: From device model to circuit simulationAli Zahir, Syed Azhar Ali Zaidi, Azzurra Pulimeno, Mariagrazia Graziano, Danilo Demarchi, Guido Masera, Gianluca Piccinini. NANOARCH 2014: 129-134 [doi]

2013

Charge distribution in a molecular QCA wire based on bis-ferrocene moleculesAzzurra Pulimeno, Mariagrazia Graziano, Ruiyu Wang, Danilo Demarchi, Gianluca Piccinini. NANOARCH 2013: 42-43 [doi]

Nanogap-based enzymatic-free electrochemical detection of glucoseIsmael Rattalino, Paolo Motto Ros, Irene Taurino, Fernando Cortes-Salazar, Gianluca Piccinini, Danilo Demarchi, Giovanni De Micheli, Sandro Carrara. biocas 2013: 130-133 [doi]

2012

UDSM Trends Comparison: From Technology Roadmap to UltraSparc Niagara2Azzurra Pulimeno, Mariagrazia Graziano, Gianluca Piccinini. tvlsi, 20(7):1341-1346, 2012. [doi]

2010

Scalable low-complexity B-spline discrete wavelet transform architectureMaurizio Martina, Guido Masera, Gianluca Piccinini. iet-cds, 4(2):159-167, 2010. [doi]

2008

Statistical power supply dynamic noise prediction in hierarchical power grid and package networksMariagrazia Graziano, Gianluca Piccinini. integration, 41(4):524-538, 2008. [doi]

2004

An electromigration and thermal model of power wires for a priori high-level reliability predictionMario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni. tvlsi, 12(4):349-358, 2004.

Effects of temperature in deep-submicron global interconnect optimization in future technology nodesMariagrazia Graziano, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni. mj, 35(10):849-857, 2004. [doi]

2003

A Block-Based Approach for SoC Global Interconnect Electrical Parameters CharacterizationM. Addino, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni. patmos 2003: 121-130 [doi]

Effects of Temperature in Deep-Submicron Global Interconnect OptimizationMario R. Casu, Mariagrazia Graziano, Gianluca Piccinini, Guido Masera, Maurizio Zamboni. patmos 2003: 90-100 [doi]

Coupled electro-thermal modeling and optimization of clock networksMario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni. mj, 34(12):1175-1185, 2003. [doi]

Novel JPEG 2000 Compliant DWT and IWT VLSI ImplementationsMaurizio Martina, Guido Masera, Gianluca Piccinini, Maurizio Zamboni. vlsisp, 35(2):137-153, 2003. [doi]

Wireless sensor networks: a power-scalable motion estimation IP for hybrid video codingFederico Quaglio, Maurizio Martina, Fabrizio Vacca, Guido Masera, Andrea Molino, Gianluca Piccinini, Maurizio Zamboni. fpga 2003: 246 [doi]

2002

Clock Distribution Network Optimization under Self-Heating and Timing ConstraintsMario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, M. M. Prono, Maurizio Zamboni. patmos 2002: 198-208 [doi]

Reconfigurable DSP IP for multimedia applicationsMaurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni. icassp 2002: 4179 [doi]

Embedded IWT evaluation in reconfigurable wireless sensor networkMaurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni. icecsys 2002: 855-858 [doi]

System architecture for error-resilient, embedded JPEG2000 wireless deliveryMaurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni. icdsp 2002: 211-218 [doi]

Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless SensorMaurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni. fpl 2002: 332-339 [doi]

Architectural strategies for low-power VLSI turbo decodersGuido Masera, M. Mazza, Gianluca Piccinini, F. Viglione, Maurizio Zamboni. tvlsi, 10(3):279-285, 2002. [doi]

2001

Synthesis of low-leakage PD-SOI circuits with body-biasingMario R. Casu, Gianluca Piccinini, Guido Masera, Maurizio Zamboni. islped 2001: 287-290 [doi]

Switching Noise Analysis Framework For High Speed Logic FamiliesMarco Delaurenti, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni. vlsid 2001: 524-530 [doi]

Hierarchical power supply noise evaluation for early power grid design predictionMariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni. slip 2001: 183-188 [doi]

JPEG 2000: finite precision representation and hardware implicationsMaurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni. icecsys 2001: 875-878 [doi]

Reconfigurable coprocessor based JPEG 2000 implementationMaurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni. icecsys 2001: 1227-1230 [doi]

2000

1999

1998

A 500 MHz 2d-DWT VLSI processorA. Brizio, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni. eusipco 1998: 1-4 [doi]

Fanout optimization under a submicron transistor-level delay modelPasquale Cocchini, Massoud Pedram, Gianluca Piccinini, Maurizio Zamboni. iccad 1998: 551-556 [doi]

1997

A comprehensive submicrometer MOST delay model and its application to CMOS buffersPasquale Cocchini, Gianluca Piccinini, Maurizio Zamboni. jssc, 32(8):1254-1262, 1997. [doi]

1996

A 650 MHz pipelined MAC for DSP applications using a new clocking strategyF. Fraternali, Guido Masera, Gianluca Piccinini, Maurizio Zamboni. eusipco 1996: 1-4 [doi]

1993

PROXIMA: PROlog eXecutIon MAchineLivio Baldi, Pierluigi Civera, Angela Iurlaro, Guido Masera, Andrea Pagni, Gianluca Piccinini, Rinaldo Poluzzi, Massimo Ruo Roch, Maurizio Zamboni. jssc, 28(3):362-370, March 1993. [doi]

1992

Deflection network: Principles, implementation, servicesGuido Albertengo, Pierluigi Civera, Renato Lo Cigno, Gianluca Piccinini, Maurizio Zamboni, Flaminio Borgonovo, Luigi Fratta, Giuseppe Panizzardi. ett, 3(2):195-206, 1992. [doi]

1989

Implementation studies for a VLSI Prolog coprocessorPierluigi Civera, Gianluca Piccinini, Maurizio Zamboni. micro, 9(1):10-23, 1989. [doi]

1987

An Experimental VLSI Prolog Interpreter: Preliminary Measurements and ResultsPierluigi Civera, F. Maddaleno, Gianluca Piccinini, Maurizio Zamboni. isca 1987: 117-126

Design considerations on a VLSI Prolog interpreterPierluigi Civera, Gianluca Piccinini, Maurizio Zamboni. jsa, 21(1-5):267-273, 1987. [doi]

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