Table of Contents

• LISA: LLM Informed Systemverilog Assertion generation with RAG and Chain-of-ThoughtSubhajit Paul, Ansuman Banerjee, Sumana Ghosh, Sudhakar Surendran, Raj Kumar Gajavelly. 1-6 [doi]
• EGaIn-Based Liquid Antennas: Beam Steering and Frequency Reconfiguration Using Microfluidic ControlSpyros Lavdas, Zafeiropoulos Konstantinos, Ktenas Athanasios, Constantinos B. Papadias. 1-6 [doi]
• Decentralized Framework for Teleportation in Quantum Core InterconnectsP. S. Rajeswari Suance, Ruchika Gupta, Maurizio Palesi, John Jose. 1-6 [doi]
• Distributed Classification with Dynamic Communication for Air Quality SensingAndrew Nash, Dirk Pesch, Krishnendu Guha. 1-6 [doi]
• A Novel Firmware Architecture leveraging Race to Sleep paradigm for Ultra-Low-Power CPSAngelos S. Voros, Evanthia Faliagka, Alexandros Spournias, Christos P. Antonopoulos, Nikos S. Voros. 1-4 [doi]
• Hardware-Accelerated On-Device Learning: Training, Partitioning, and Compilation for Constrained Edge AIIuliia Topko, Alexey Serdyuk, Tanja Harbaum, Jürgen Becker 0001. 1-6 [doi]
• VFMA: Scalable Floating-Point Accelerator for Vector FMA on FPGAsHimanshu Rai, Sasi Snigdha Yadavalli, Aishwarya Sridhar, Nanditha Rao. 1-6 [doi]
• AnaIR: A Semi-Analytical Green's Function Inspired Neural Network for Static IR Drop PredictionShruti Pandey, Aneeket Yadav, Smruti R. Sarangi. 1-6 [doi]
• Flip-UnLock: An Anomaly Detection Attack on Flip-Flop-Based Logic LockingArmin Darjani, Nima Kavand, Akash Kumar 0001. 1-6 [doi]
• Carbon-Efficient 3D DNN Acceleration: Optimizing Performance and SustainabilityAikaterini Maria Panteleaki, Konstantinos Balaskas, Georgios Zervakis 0001, Hussam Amrouch, Iraklis Anagnostopoulos. 1-6 [doi]
• Hybrid Bayesian Optimization with Early Termination Strategies for Auto TuningHsiang-Cheng Hsieh, ShengPo Lin, Arbind Kumar Mahto, Kuei-Chung Chang, Juin-Ming Lu, Tay-Jyi Lin, Tien-Fu Chen. 1-6 [doi]
• Energy-Efficient Digital Design: A Comparative Study of Event-Driven and Clock-Driven Spiking NeuronsFilippo Marostica, Alessio Carpegna, Alessandro Savino, Stefano Di Carlo. 1-6 [doi]
• Energy-Efficient Basecalling for ONT Long Reads on a Hybrid ASIC-GPU PlatformCheng-You Tsai, Hung-Yu Tseng, Po-Yen Chang, Yi-Chang Lu. 1-6 [doi]
• A 6T SRAM based reconfigurable in-memory XOR/XNOR and accumulation architectureCheena Singhal, Sparsh Mittal. 1-6 [doi]
• HardObfSec: Measuring Hardware Obfuscation Security at RTLSonam Sharma, Dipanjan Roy, Digambar Pawar. 1-6 [doi]
• Adaptive Multi-Precision Inference for Large-Scale AI Using IEEE P3109 FP8Arnav Ramamoorthy, Kiran K. Gunnam. 1-2 [doi]
• UltraLiM: In-Memory Boolean Logic Architecture Using UltraRAMShamiul Alam, Kazi Asifuzzaman, Ahmedullah Aziz. 1-6 [doi]
• Motion Detection over 5G through Sensing Signal Disturbance Analysis leveraging COTS platformIoannis T. Rekanos, Evanthia Faliagka, Michael Paraskevas, Vaggelis Kapoulas, Christos P. Antonopoulos, Nikos S. Voros. 1-6 [doi]
• A Multi-Scale Lightweight 1D-CNN for Efficient CAN Intrusion DetectionXuke Yan, Linxi Zhang. 1-6 [doi]
• State Dependent Optimization with Quantum Circuit CuttingXinpeng Li, Ji Liu 0007, Jeffrey M. Larson, Shuai Xu, Sundararaja Sitharama Iyengar, Paul D. Hovland, Vipin Chaudhary. 1-6 [doi]
• A Width-Configurable Hardware Approach for Accelerating Fixed-Point SimulationKeyvan Shahin, Michael Hübner 0001, Christian Herglotz. 1-6 [doi]
• PACE: An Optimal Piecewise Polynomial Approximation Unit for Flexible and Efficient Transformer Non-linearity AccelerationArpan Suravi Prasad, Gamze Islamoglu, Luca Bertaccini, Davide Rossi, Francesco Conti 0001, Luca Benini. 1-6 [doi]
• Hierarchical Optimization of Karatsuba Multipliers for ECDSA Hardware AcceleratorsPruthvi Parate, Daksh Sharma, Alwin Shaju, Madhav Rao. 1-6 [doi]
• CIM for Transformer Models: Enhancing Large Language Model Inference EfficiencyMeng-Syuan Li, Jung-Fang Ke, En-Ming Huang, Zhi-Wei Liu, Yu-Guang Chen, Chun-Yi Lee. 1-6 [doi]
• An Event-Based Gate-Level Framework for Power Side-Channel Leakage AssessmentKatayoon Basharkhah, Zahra Hojati, Zainalabedin Navabi. 1-6 [doi]
• Efficient Multi-Cycle Folded Integer MultipliersAhmad Houraniah, H. Fatih Ugurdag, Cengiz Emre Dedeagac. 1-6 [doi]
• Memory Wall is not gone: A Critical Outlook on Memory Architecture in Digital Neuromorphic ComputingAmirreza Yousefzadeh, Sameed Sohail, Ana Lucia Varbanescu. 1-4 [doi]
• AxEnMULT: Design of an Efficient and Reliable Approximate Encoding-Based MultiplierAhsan Rafiq, Alberto Bosio, Salvatore Pappalardo, Maksim Jenihhin. 1-6 [doi]
• A Vertical Approach to Designing and Managing Sustainable Heterogeneous Edge Data CentersAikaterini Maria Panteleaki, Varatheepan Paramanayakam, Vasileios Pentsos, Andreas Karatzas, Spyros Tragoudas, Iraklis Anagnostopoulos. 1-6 [doi]
• Quantum-Enhanced Classification of Brain Tumors Using DNA Microarray Gene Expression ProfilesEmine Akpinar, Batuhan Hangün, Murat Oduncuoglu, Oguz Altun, Önder Eyecioglu, Zeynel Yalcin. 1-6 [doi]
• Parametric RISC-V Compliant Floating-Point Arithmetic and Conversion CircuitsSpyros Chalkias, Anastasis Avgoustidis, Thomas Noulis, Georgios Keramidas, Vasilis F. Pavlidis. 1-6 [doi]
• Dynamic Early-Exit Convolutional Neural Networks for Edge Vision: The Benefits, The Challenges, and the Road AheadMichalis Piponidis, Georgios Konstantinidis 0003, Maria K. Michael, Theocharis Theocharides. 1-6 [doi]
• GAAMP: Automatic Thread Count/Affinity and DVFS Tuning for Asymmetric MulticoresMarcelo K. Moori, Arthur Francisco Lorenzon, Hiago Mayk G. de A. Rocha, Antonio Carlos S. Beck. 1-6 [doi]
• RaptorQu: Electromagnetic Modeling of SuperconductorsKonstantinos Nikellis, Garth Sundberg, Yiannis Moisiadis, Stefanos Stefanou. 1-6 [doi]
• Evaluating the Scalability of Binary and Ternary CNN Workloads on RRAM-based Compute-in-Memory AcceleratorsJosé Cubero-Cascante, Rebecca Pelke, Noah Flohr, Arunkumar Vaidyanathan, Rainer Leupers, Jan Moritz Joseph. 1-6 [doi]
• Breaking Down Quantum Compilation: Profiling and Identifying Costly PassesFelix Zilk, Alessandro Tundo, Vincenzo De Maio, Ivona Brandic. 1-6 [doi]
• Efficient Deployment of Very Wide and Very Deep Hypersparse FFNs on FPGAParamdeep Singh, David C. Anastasiu. 1-6 [doi]
• Boosting Scan Chain Security in a White-box through Restricted Pattern FilteringLeon Li, Alex Orailoglu. 1-6 [doi]
• MADel0: A Modelling and Assessment Framework for Delay PUFs leveraging Gradient-based Optimization TechniquesDurba Chatterjee, Debdeep Mukhopadhyay, Aritra Hazra. 1-7 [doi]
• AI-enabled Application Process Interface for On-device Personalized Blood Pressure MonitoringRajdeep Kumar Nath, Daniel Nguyen, Mohammad H. Behfar, Mari Rytky, Teemu Ahmaniemi, Johan Plomp. 1-6 [doi]
• FF-GFA: Flipped Folded Architecture enabled Power- and Area-Efficient Gabor Filter DesignPriyanka Agarwal, Pruthvi Parate, Madhav Rao. 1-6 [doi]
• A Parameterizable Convolution Accelerator for Embedded Deep Learning ApplicationsPanagiotis Mousouliotis, Georgios Keramidas. 1-6 [doi]
• Configurable Hardware Module for Low-Power Coding in Heterogeneous-Monolithic 3D NoC LinksAdriano Lopes Pata, Nithya Raj, Alberto García Ortiz. 1-6 [doi]
• A 4.8ps Resolution, PVT-insensitive Vernier-based TDC using switched-RO PLL and Back Gate CalibrationPatroklos Pazionis, Andreas Tsimpos, Gerasimos Theodoratos, Georgios Panagopoulos. 1-6 [doi]
• X-HEEP: An Open-Source, Configurable and Extendible RISC-V Platform for TinyAI ApplicationsSimone Machetti, Pasquale Davide Schiavone, Giovanni Ansaloni, Miguel Peón Quirós, David Atienza. 1-6 [doi]
• Efficient Tree Architecture for the Design of Static CMOS Magnitude ComparatorsConstantinos Efstathiou, John Liaperdos, Yiorgos Tsiatouhas. 1-6 [doi]
• Real-time Padel Strokes ClassificationGeorgios Papaspyropoulos, Evanthia Faliagka, Theodoros Skandamis, Christos P. Antonopoulos, Nikos S. Voros. 1-4 [doi]
• On-the-fly Validation of Hierarchical Cache Coherence Protocols using Directed TestingAbhinaba Chakraborty, Ansuman Banerjee, Vinay B. Y. Kumar, Arindam Mallik. 1-6 [doi]
• Designing Compatible Analog Circuits for Equilibrium Propagation: Implementations Using The Adjoint Method and Reciprocity PrinciplesMohamed Watfa, Alberto García Ortiz, Gilles Sassatelli. 1-6 [doi]
• Catwalk: Unary Top-K for Efficient Ramp-No-Leak Neuron Design for Temporal Neural NetworksDevon Lister, Prabhu Vellaisamy, John Paul Shen, Di Wu. 1-6 [doi]
• Enabling fully connected probabilistic computing through a fast pipelined multi-operand adderGiacomo Orlandi, Christian Conti, Marco Vacca, Mariagrazia Graziano, Fabrizio Riente. 1-6 [doi]
• Automating Versatile Time-Series Analysis with Tiny Transformers on Embedded FPGAsTianheng Ling, Chao Qian 0009, Lukas Johannes Haßler, Gregor Schiele. 1-6 [doi]
• iLog 3.0: Estimating Food Volume from 2D Images Using Mask R-CNN and Monocular Depth EstimationIndira Devi Siripurapu, Alakananda Mitra, Saraju P. Mohanty, Elias Kougianos. 1-6 [doi]
• Machine Learning Fault Injection Detection in Clock Signals: An Analysis of Frequency ImpactAsier Gambra, Unai Rioja, Durba Chatterjee, Igor Armendariz, Lejla Batina. 1-6 [doi]
• SRAM Beyond FinFET: Performance and Aging Challenges in Nanosheet and CFETMahdi Benkhelifa, Hussam Amrouch. 1-6 [doi]
• ASIC Design Flow Using Simulink and Cadence Digital IC Design ToolsCharanya K. Rao, Ashmitha Talluri, Ava Hedayatipour. 1-5 [doi]
• Application Specific Hardware-Algorithm Metric Analysis for Vision based In-Sensor ComputingSubhradip Chakraborty, Kapish Singh, Ankur Singh, Zihan Yin, Akhilesh Jaiswal 0001. 1-6 [doi]
• PRIVATEER: Secure FPGA Acceleration for 6G AI Edge AnalyticsAimilios Leftheriotis, Ilias Papalamprou, Apostolos Garos, Georgios Gardikis, Maria Christopoulou, George Xilouris, Georgios Livanos, Nikolaos Papadakis, Dimosthenis Masouros, George Theodoridis, Dimitrios Soudris. 1-6 [doi]
• gem5-SysXelerator: A Full-System Simulator for Accelerator ArchitecturesSebastian Fischer, Nithya Raj, Alberto García Ortiz. 1-6 [doi]
• Retrospective: A CORDIC Based Configurable Activation Function for NN ApplicationsOmkar Kokane, Gopal Raut, Salim Ullah, Mukul Lokhande, Adam Teman, Akash Kumar 0001, Santosh Kumar Vishvakarma. 1-6 [doi]
• Approximate Redundant Booth Multiplier Based on Error Compensation MechanismJiashuo Zhang, Hongge Li, Xinyu Zhu, Yinjie Song, Yumeng Liu. 1-6 [doi]
• Stella Nera: A Differentiable Maddness-Based Hardware Accelerator for Efficient Approximate Matrix MultiplicationJannis Schönleber, Lukas Cavigelli, Matteo Perotti, Luca Benini, Renzo Andri. 1-6 [doi]
• Autonomously Reconfigurable Telemetry and Monitoring System for CubeSatsChristoforos Vasilakis, Alexandros Tsagkaropoulos, Angelos Motsios, Dionysios I. Reisis. 1-5 [doi]
• Technology and Power-aware Investigation of Nanostructures for Molecular Field-Coupled NanocomputingElena Ferrero, Federico Ravera, Roberto Listo, Yuri Ardesi, Gianluca Piccinini, Mariagrazia Graziano. 1-6 [doi]
• A Novel Architecture using Dynamic Computing Nodes to Improve Multi-Access Edge Cluster ProductivityBiswadeep Chatterjee, Swagata Mandal, Amlan Chakrabarti, Sayan Chatterjee. 1-6 [doi]
• VegeCare: An IoT Framework To Monitor and Maintain Vegetable QualityMahdi Shamsa, Laavanya Rachakonda, Saraju P. Mohanty, Elias Kougianos. 1-6 [doi]
• Design and Hardware Implementation of a PRNG-CS for Embedded Security ApplicationsMahieddine Anouar Hadjadj, Redouane Kaibou, Said Sadoudi. 1-4 [doi]
• Sparse-Aware NTT: Accelerating Lattice-Based Cryptography on FPGAsDixit Dutt Bohra, Dip Sankar Banerjee, Somitra Sanadhya. 1-6 [doi]
• An Event Autoencoder for High-Speed Vision SensingRiadul Islam, Joey Mulé, Dhandeep Challagundla, Shahmir Rizvi, Sean Carson. 1-6 [doi]
• RAT: RFET-based Analog Hardware TrojanNima Kavand, Armin Darjani, Tushar Niranjan, Akash Kumar 0001. 1-6 [doi]
• A Quasi Fat Tree-based Formation of Micro-Programmable Processing Elements for Machine Learning ApplicationsSepideh Kheirollahi, Sinatra Babele Khanshan, Zainalabedin Navabi. 1-4 [doi]
• FPGA Implementation of a Fixed-Point Arctangent Function Using Harmonized Parabolic SynthesisYassin Atwa, Süleyman Savas. 1-5 [doi]
• A Theoretical Framework For Modeling Cache-based Side-Channel Attacks and CountermeasuresNivedita Shrivastava, Smruti R. Sarangi. 1-6 [doi]
• Bistable All-Josephson Junction SQUID with Dual Φ-Junctions for State-Controlled Superconducting CircuitsAyisat Adedokun, Yerzhan Mustafa, Selçuk Köse. 1-6 [doi]
• Efficient Implementation of RISC-V Vector Permutation InstructionsVasileios Titopoulos, George Alexakis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos. 1-6 [doi]
• n-4 arithmetic unitsDimitris Bakalis, Haridimos T. Vergos. 1-5 [doi]
• Quantum Properties Trojans (QuPTs) for Attacking Quantum Neural NetworksSounak Bhowmik, Travis S. Humble, Himanshu Thapliyal. 1-6 [doi]
• TQHD: Thermometer Encoding Based Quantization for Hyperdimensional ComputingCaio Vieira, Jerónimo Castrillón, Antonio Carlos Schneider Beck. 1-6 [doi]
• High-Precision BGR Design with Advanced Curvature Compensation & Optimized Layout in 28 nm CMOS TechnologyRavi S. Siddanath, Mohit Gupta, R. Dhirendra Rao, Souvik Kumar Das, Raghavendra Manjunath Hegde, Prasanna Kumar Misra, Manish Goswami, Kavindra Kandpal. 1-6 [doi]
• Towards Improving Performance Metrics of Minority Majority Inverter Graph (mMIG) CircuitsMrunal Shende, Bodhisatwa Mazumdar. 1-6 [doi]
• From Pixels to Reasoning: A Cross-Layer Photonic Design for Edge Visual IntelligenceDeniz Najafi, Mehrdad Morsali, Hamza Errahmouni Barkam, Brendan Reidy, Sepehr Tabrizchi, Arman Roohi, Mahdi Nikdast, Ramtin Zand, Mohsen Imani, Shaahin Angizi. 1-6 [doi]
• Efficient Neural Network Compression for Fast Inference on HardwareJingcun Wang, Mengnan Jiang, Grace Li Zhang. 1-2 [doi]
• Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-VAlperen Bolat, Sakir Sezer, Kieran McLaughlin, Henry Hui. 1-6 [doi]
• Optimization and Security of AI Models for Deployment at Edge: A Comprehensive ReviewHafizur Rahaman 0001, Chandan Giri, Surajit Kumar Roy, Amlan Chakrabarti. 1-6 [doi]
• Advancing Edge Analog Processing with Photonic In-Memory ComputingMahdi Nikdast. 1 [doi]
• Optimization of Quantum Error Correcting Code under Temporal Variation of Qubit QualitySubrata Das, Swaroop Ghosh. 1-6 [doi]
• Q-Fusion: Diffusing Quantum CircuitsCollin Beaudoin, Swaroop Ghosh. 1-6 [doi]
• SynAssert: Automated Synthesis of CSCA Leakage Patterns into Cost-Effective Security AssertionsAli Azarpeyvand, Mohammad Eslami, Gert Jervan, Jaan Raik, Tara Ghasempouri. 1-6 [doi]
• Optimizing TCN Inference: A Hardware-Software Co-Design Approach with CGRA AccelerationAlessandro Varaldi, Alessio Naclerio, Fabrizio Riente, Maurizio Zamboni, Mariagrazia Graziano, Marco Vacca. 1-6 [doi]
• A PUF-Enhanced Ring Oscillator-Based Authentication System for IoT DevicesMaryam Esmaeilian, Louis Morge-Rollet, David Hély, Elena Ioana Vatajelu, Romain Siragusa. 1-6 [doi]
• Tournament Cache Decay: Tight Control of Leakage Power for Last-Level CachesTheodoros Papavasileiou, Georgios Keramidas, Vasilis F. Pavlidis. 1-6 [doi]
• EXAMINER: IP Extraction Algorithm from MAGIC Logic-in-MemoryLorenzo Pfeifer, Rainer Leupers, Jan Moritz Joseph. 1-6 [doi]
• Joint Compression Strategies for CNNs: A Case Study on Low Rank Factorization, Filter-based Pruning and Unstructured PruningMilad Kokhazadeh, Georgios Keramidas, Vasilios I. Kelefouras. 1-6 [doi]
• Assessing Gaston: Side-channel Security and Hardware Cost Comparison with Ascon-pParisa Amiri-Eliasi, Silvia Mella, Lejla Batina. 1-6 [doi]
• HMR-NEureka: Hybrid Modular Redundancy DNN Acceleration in Heterogeneous RISC-V SoCsLuigi Ghionda, Riccardo Tedeschi, Yvan Tortorella, Arpan Suravi Prasad, Davide Rossi, Luca Benini, Francesco Conti 0001. 1-6 [doi]
• 3DPlace: Timing-driven Detailed Placement for Monolithic 3D ICsDimitrios Vamvakidis, Christos Georgakidis, Aikaterini Tsilingiri, Nikolaos Sketopoulos, Christos P. Sotiriou, Vasilis F. Pavlidis. 1-6 [doi]
• Quantum Circuit Synthesis of an Approximate Hybrid Kolmogorov-Arnold NetworkShion Samadder Chaudhury, Sudhindu Bikash Mandal, Turbasu Chatterjee, Arnav Das 0002, Amlan Chakrabarti. 1-6 [doi]
• MASH Digital Delta-Sigma Modulators for the CMOS Qubit ControllerHyunyoung Yoo, Muhammad Fakhri Mauludin, Yeonsu Kim, Su-Hyeon Kim, Eun-Ji Yoo, Jae-Yun Park, Jusung Kim, Jae-Won Nam. 1-2 [doi]
• Bio-Inspired Computing with Emerging Devices: Bridging 2D Materials and Neuromorphic ArchitecturesMatteo Farronato, Piergiulio Mannocci, Alessandro Milozzi, Christian Monzio Compagnoni, Daniele Ielmini. 1 [doi]
• Analytical Approach to Engineer Strain-Gradient for Magnetic Skyrmion-based LeakyIntegrate and Fire Neuronal DynamicsRavish Kumar Raj, Arun Kumar, Yasser Rezaeiyan, Pernille Klarskov, Farshad Moradi, Sonal Shreya. 1-6 [doi]
• Architecture, Simulation and Software Stack to Support Post-CMOS Accelerators: The ARCHYTAS ProjectGiovanni Agosta, Stefano Cherubin, Derek Christ, Francesco Conti 0001, Asbjørn Djupdal, Matthias Jung 0001, Georgios Keramidas, Roberto Passerone, Paolo Rech, Elisa Ricci 0001, Philippe Velha, Flavio Vella, Kasim Sinan Yildirim, Nils Wilbert. 1-6 [doi]
• Sustainable AI in the Cloud-to-Thing Continuum: A Bibliometric Review on Lightweight, Small-Sample, and Federated Learning ApproachesSian Lun Lau, Saad Aslam, Amlan Chakrabarti, Jari Porras. 1-6 [doi]
• Accelerating Equation Solvers using Gauss-Jacobi on Multi-FPGA Systems with Ring NoCShruti Patkar, Harsh, Souraja Kundu, Gaurav Trivedi. 1-4 [doi]
• Efficient Logic Evaluation Using RRAM-Based In-Memory ComputingShuhang Zhang. 1-6 [doi]
• Resource-Efficient LSTM Architecture for Keyword Spotting with CORDIC-Activation ApproximationAbhishek Yadav, Ayush Dixit, Utsav Jana, Masahiro Fujita, Binod Kumar 0001. 1-6 [doi]
• Invited: A Hardware-Algorithm Vision for In-Sensor IntelligenceChengwei Zhou, Gourav Datta. 1-2 [doi]
• FlatAttention: Dataflow and Fabric Collectives Co-Optimization for Efficient Multi-Head Attention on Tile-Based Many-PE AcceleratorsChi Zhang, Luca Colagrande, Renzo Andri, Thomas Benz, Gamze Islamoglu, Alessandro Nadalini, Francesco Conti 0001, Yawei Li 0001, Luca Benini. 1-6 [doi]
• New Branching Heuristics for Incremental Bounded Model CheckingSatyam Shubham, Sutirtha Bhattacharyya, Ansuman Banerjee, Raj Kumar Gajavelly. 1-6 [doi]
• Reliable, Secure, and Spectrally Efficient ISAC using Distributed Multiuser MIMO and Non-Orthogonal WaveformTongyang Xu, Christos Masouros, Izzat Darwazeh. 1-6 [doi]
• Dynamic Mitigation of Hardware Trojan Induced Black Hole Router Attack in Network-on-ChipGunjan Dhanuka, Syam Sankar, John Jose. 1-6 [doi]
• CHIMERA: Cryptographic Hardware for Integrated Multipurpose Engine on RISC-V with ASCONAlessandra Dolmeta, Valeria Piscopo, Maurizio Martina, Guido Masera. 1-6 [doi]
• A Low-Complexity XOR-Based BCH Decoder for PAM4 Modulation SystemsChangfu He, Xinle Jia, Yuxing Chen, Wenli Xu, Suwen Song, Zhongfeng Wang 0001. 1-6 [doi]
• Universal Topological Arrays: An Efficient Solution for Provably Secure HardwareDeepali Garg, Lawrence T. Pileggi. 1-6 [doi]
• LiteViT: Leveraging the Power of Transformers for Edge AI in Crop Disease ClassificationSai Mahesh Mudavat, Alakananda Mitra, Saraju P. Mohanty, Elias Kougianos. 1-6 [doi]
• Hardware-Optimized RNN Detection for Insertion/Deletion Channels in Wireless CommunicationMatthias Nickel, Lester Kalms, Julian Haase, Jieyu Zhao, Diana Göhringer. 1-6 [doi]
• Support Vector Machines Classification on Bendable RISC-VPolykarpos Vergos, Theofanis Vergos, Florentia Afentaki, Konstantinos Balaskas, Georgios Zervakis 0001. 1-6 [doi]
• Enabling Real-Time Streaming Temporal Convolution Network Inference on Ultra-Low-Power MicrocontrollersSeyed Ahmad Mirsalari, Marco Fariselli, Léo Bijar, Francesco Paci, Luca Benini, Giuseppe Tagliavini. 1-6 [doi]
• SanaSolo 3.0: A Low-Ground, IoT-Based Rover for In-Situ Soil Fertility MonitoringLaavanya Rachakonda, Samuel Stasiewicz. 1-6 [doi]
• HW/SW Formal Co-Verification of Rust-based Designs Using Hardware Abstraction ModelSascha Neske, Bryan Olmos, Shuhang Zhang, Martin Kröning, Stefan Lankes, Wolfgang Kunz, Djones Lettnin. 1-6 [doi]
• Unlocking the Benefits of Dynamic Quantum Circuits in Resource Constraint ArchitectureAbhoy Kole, Mohammed E. Djeridane, Arighna Deb, Kamalika Datta, Indranil Sengupta 0001, Rolf Drechsler. 1-6 [doi]
• n-1 Adder DesignConstantinos Efstathiou, Ioannis Kouretas, Paris Kitsos. 1-6 [doi]
• Digital IC Design of a 45nm CMOS Chua Encryption Architecture for Resource Limited DevicesCharanya K. Rao, Ravi Monani, Ava Hedayatipour. 1-6 [doi]
• High-Performance FPGA-Based Accelerator of L-BFGS for 3D Face ReconstructionHaoran Pan, Bohang Xiong, Jing Tian 0004, Shikun Zhang, Hao Zhu 0004, Zhongfeng Wang 0001. 1-6 [doi]
• Accelerating Solar Spectra Analysis:A High-Performance FPGA Framework with Parameterized FiltersVerjina Torosian Khouygani, Shahnam Mirzaei, Christian Beck, Debi Prasad Choudhary. 1-6 [doi]
• Quantum-enhanced optimization for patient stratification in clinical trialsLaia Domingo, Christine Johnson. 1 [doi]
• Leveraging Low-Rank Factorization for Compressing DNN Speech Enhancement ModelsZahra Kokhazad, Milad Kokhazadeh, Georgios Keramidas, Vasilios I. Kelefouras. 1-5 [doi]
• Emotion Recognition in Older Adults with Quantum Machine Learning and Wearable SensorsMd. Saif Hassan Onim, Travis S. Humble, Himanshu Thapliyal. 1-6 [doi]
• PV-Clock: Process Variation-Aware 3D Clock Network Synthesis for Robust and Power-Efficient Timing OptimizationYiyu Wang, Vasilis F. Pavlidis, Rui Wang, Yuanqing Cheng. 1-6 [doi]
• Inductive Effect-Aware Power Distribution Network Modeling and Analysis for Heterogeneous 3D Integrated CircuitsQuansen Wang, Vasilis F. Pavlidis, Xuning Feng, Rui Wang, Wei Zhang, Yuanqing Cheng. 1-6 [doi]
• Accelerating Layout Automation Using AI-Driven Smart Routing for Custom Circuit DesignAva Hedayatipour, Pouya Motakef. 1-2 [doi]
• Scalable and Power-Efficient Merging Network Design: Automatic RTL Generation for FPGAArdhendu Sarkar, Sriparna Mandal, Surajeet Ghosh. 1-6 [doi]
• TiAS: Time Aware Split Computing to Secure AI/ML Workloads for FPGA based Edge Platforms against Unintentional DelaysKrishnendu Guha. 1-6 [doi]
• FastMamba: A High-Speed and Efficient Mamba Accelerator on FPGA with Accurate QuantizationAotao Wang, Haikuo Shao, Shaobo Ma, Zhongfeng Wang 0001. 1-6 [doi]
• Quantum-Chiplet: A VLSI-Like Methodology for Hierarchical Quantum Design and VerificationHao-Yu Lu, Yu-Ting Kao, Yeong-Jar Chang, Jason Gemsun Young, Darsen D. Lu. 1-5 [doi]
• Dataset Distillation for Quantum Neural NetworksKoustubh Phalak, Junde Li, Swaroop Ghosh. 1-5 [doi]
• Synthesis-Aware Area Optimization for Safety Registers in Automotive SoCsShuhang Zhang, Bryan Olmos, Wolfgang Kunz, Djones Lettnin. 1-6 [doi]
• HEDGY: Heterogeneous Design Management for Multi-Tenant Multi-FPGA Edge SystemsIan Kersz, Arthur F. Ely, Pedro Alles, Michael G. Jordan, José Rodrigo Azambuja, Fernanda L. Kastensmidt, Antonio Carlos S. Beck. 1-6 [doi]
• Flexible Hardware Accelerators for Ultra-Low Power Edge AI: The CONVOLVE ApproachPanagiotis Chaidos, Alexios Maras, Georgios Alexandris, Xiaoling, Asmae El Arrassi, Bas Ahn, James D. Garside, Yunhao Deng, Theofilos Spyrou, Anteneh Gebregiorgis, Mottaqiallah Taouil, Manil Dev Gomony, Sotirios Xydis, Marian Verhelst, Said Hamdioui, Dimitrios Soudris, Henk Corporaal. 1-6 [doi]
• Aging Model Development for ASAP 7 nm Predictive PDK: Application in Aging-Aware Performance Prediction of Digital Logic and ADCs in Data Acquisition SystemNeha Gupta, Lomash Chandra Acharya, Mahipal Dargupally, Khoirom Johnson Singh, Amit Kumar Behera, Johan Euphrosine, Sudeb Dasgupta, Anand Bulusu. 1-4 [doi]
• A Sampling-based Method for Output Safety Verification of Spiking Neural NetworksSruti Goswami, Ansuman Banerjee, Swarup Kumar Mohalik. 1-6 [doi]
• Comparative Analysis of QNN Architectures for Wind Power Prediction: Feature Maps and Ansatz ConfigurationsBatuhan Hangün, Emine Akpinar, Oguz Altun, Önder Eyecioglu. 1-6 [doi]
• Ultra-Low-Latency Data Link Layer TX Buffer Architecture for Wireless CommunicationsHendrik Borchert, Karthik KrishneGowda, Milos Krstic. 1-6 [doi]
• Tunable Approximate Booth MultiplierIoannis Rizos, Georgios Papatheodorou, Aristides Efthymiou. 1-6 [doi]
• PUF-ML: Machine Learning - Based Physical Unclonable Functions For Cost Effective Integration In Smart HealthcareVenkata P. Yanambaka, Jian Zhang, Jonathan Gratch, Kahlan Edwards. 1-6 [doi]
• Low-Cost FlashAttention with Fused Exponential and Multiplication Hardware OperatorsKosmas Alexandridis, Vasileios Titopoulos, Giorgos Dimitrakopoulos. 1-6 [doi]
• A Decomposition Method for MCT Gates Considering T-depth of Each QubitZanhe Qi, Kouki Hirono, David Clarino, Shigeru Yamashita. 1-6 [doi]
• MSDF-Based Hardware Accelerators for Energy-Efficient Neural Networks in Edge Computing ApplicationsSahar Moradi Cherati, Leonel Sousa. 1-4 [doi]
• Towards Future 6G Telecommunications: Research at the THz Domain in Intracom TelecomDimitrios C. Tzarouchis, Evangelos Pikasis, Elias D. Tsirbas, Eleftherios C. Loghis, Sotirios Aloimonos, Vassilis Koratzinos, Dimitrios Bastas, Dimitrios Kritharidis, José Luis González-Jiménez, Antonio Clemente, Francesco Foglia Manzillo, Alexandre Siligaris, Sean Ahearne, Thomas Merkle. 1-4 [doi]
• Approximate Swish Activation Function for Low-Energy Yet Low-Error VLSI ImplementationsFanny Spagnolo, Stefania Perri, Pasquale Corsonello. 1-5 [doi]
• A Secure and Sustainable RISC-V Processor with Intrinsic PUF for Edge AITarun Sharma, Deepank Grover, Sujay Deb. 1-6 [doi]
• SAGE: Shapley Attention Graph nEtwork for Gate-level Trojan Detection and LocalizationZhixin Pan, Ziyu Shu, Xinrui Yu. 1-6 [doi]
• ChatTCAD: Leveraging Large Language Models for Automated TCAD Simulation File GenerationZhe Zhang, Sani R. Nassif, Mehdi B. Tahoori. 1-6 [doi]
• Real-Time Person Recognition Using MoveNet for Pose-Based IdentificationEvanthia Faliagka, George Tefas, Christos P. Antonopoulos, Nikos S. Voros. 1-4 [doi]
• Towards the Optimization of Hardware Efficiency through Machine LearningHeba Khdr, Mohammed Bakr Sikal, Benedikt Dietrich, Jörg Henkel. 1-6 [doi]
• InsectAgent: Improving Insect Recognition through Dynamic Information Augmentation with Multimodal Large Language ModelsShu Zhao, Ajay Narayanan Sridhar, Harland M. Patch, Vijaykrishnan Narayanan. 1-6 [doi]
• Watermarking Edge Neural Network for Object DetectionXiaoxu Peng, Tu Anh Ngo, Farrel Koh, Anupam Chattopadhyay. 1-6 [doi]
• Boundary-Power Overlapped Design for Sub-3nm Standard Cell PlacementJaeha Lee, Woonseon Cheon, Yunseok Noh, Huijae Lim, Subin Jin, ShinWoo Kim, Hayoung Kim, Sanghoon Baek. 1-6 [doi]
• Enhancing Performance of Floating Point Units Using Parallel Prefix AddersAndreas-Efstathios Eleftheriadis, Thomas Noulis, Georgios Keramidas, Vasilis F. Pavlidis. 1-6 [doi]
• PolyFHEmus: Rethinking Multiplication in Fully Homomorphic EncryptionCharles Gouert, Nektarios Georgios Tsoutsos. 1-6 [doi]