Abstract is missing.
- Branch Folding in the CRISP Microprocessor: Reducing Branch Delay to ZeroDavid R. Ditzel, Hubert R. McLellan. 2-9
- An Evaluation of Branch ArchitecturesJohn A. DeRosa, Henry M. Levy. 10-16
- Checkpoint Repair for Out-of-order Execution MachinesWen-mei W. Hwu, Yale N. Patt. 18-26
- Instruction Issue Logic for High-Performance, Interruptable Pipelined ProcessorsGurindar S. Sohi, Sriram Vajapeyam. 27-34
- Fast Temporary Storage for Serial and Parallel ExecutionJohn A. Swensen, Yale N. Patt. 35-43
- Performance Analysis and Design of a Logic Simulation MachineKenneth F. Wong, Mark A. Franklin. 46-55
- A Modular Systolic Architecture for Image ConvolutionsKshitij Doshi, Peter J. Varman. 56-63
- A Template Matching Algorithm Using Optically-Connected 3-D VLSI ArchitectureSatoshi Fujita, Reiji Aibara, Masafumi Yamashita, Tadashi Ae. 64-70
- Mapping Data Flow Programs on a VLSI Array of ProcessorsBilha Mendelson, Gabriel M. Silberman. 72-80
- Analytical Modeling and Architectural Modifications of a Dataflow ComputerDipak Ghosal, Laxmi N. Bhuyan. 81-89
- A Unified Resource Management and Execution Control Mechanism for Data Flow MachinesMasaru Takesue. 90-97
- High Performance Integrated Prolog Processor IPPShigeo Abe, Tadaaki Bandoh, S. Yamaguchi, Ken-ichi Kurosawa, Kaori Kiriyama. 100-107
- Performance Studies of a Parallel Prolog ArchitectureBarry S. Fagin, Alvin M. Despain. 108-116
- An Experimental VLSI Prolog Interpreter: Preliminary Measurements and ResultsPierluigi Civera, F. Maddaleno, Gianluca Piccinini, Maurizio Zamboni. 117-126
- Deterministic and Stochastic Modeling of Parallel Garbage Collection -- Towards Real-Time CriteriaOlivier Ridoux. 128-136
- The Sharing of Environment in AND-OR-Parallel Execution of Logic ProgramsChengzheng Sun, Tzu Yungui. 137-144
- Architectural Issues in Designing Symbolic Processors in OpticsAloke Guha, Raja Ramnarayan, Matthew Derstine. 145-151
- Rearrangeability of Multistage Shuffle/Exchange NetworksAnujan Varma, C. S. Raghavendra. 154-162
- Optimized Mesh-Connected Networks for SIMD and MIMD ArchitecturesRamón Beivide, Enrique Herrada, José L. Balcázar, Jesús Labarta. 163-170
- Performance Evaluation of Reduced Bandwidth Multistage Interconnection NetworksDavid T. Harper III, J. Robert Jump. 171-175
- Hardware Support for Interprocess CommunicationUmakishore Ramachandran, Marvin H. Solomon, Mary K. Vernon. 178-188
- Architecture of a Message-Driven ProcessorWilliam J. Dally, Linda Chao, Andrew A. Chien, Soha Hassoun, Waldemar Horwat, Jon Kaplan, Paul Song, Brian Totty, D. Scott Wills. 189-196
- Effect of Storage Allocation/Reclamation Methods on Parallelism and Storage RequirementsManoj Kumar. 197-205
- Cache Design of a Sub-Micron CMOS System/370J. H. Chang, H. Chao, Kimming So. 208-213
- An Architectural Perspective on a Memory Access ControllerMartin Freeman. 214-223
- Organization and Analysis of a Gracefully-Degrading Interleaved Memory SystemKifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan. 224-231 [doi]
- Correct Memory Operation of Cache-Based MultiprocessorsChristoph Scheurich, Michel Dubois. 234-243
- Hierarchical Cache/Bus Architecture for Shared Memory MultiprocessorsAndrew W. Wilson Jr.. 244-252
- Multiprocessor Cache Design ConsiderationsRoland L. Lee, Pen-Chung Yew, Duncan H. Lawrie. 253-262
- Performance Evaluation of Multiple Register SetsRichard J. Eickemeyer, Janak H. Patel. 264-271
- A Performance Analysis of Automatically Managed Top of Stack BuffersTimothy J. Stanley, Robert G. Wedig. 272-281
- Concepts of the System/370 Vector ArchitectureBrian B. Moore, Andris Padegs, Ronald M. Smith, Werner Buchholz. 282-288 [doi]
- WISQ: A Restartable Architecture Using QueuesAndrew R. Pleszkun, James R. Goodman, Wei-Chung Hsu, R. T. Joersz, George E. Bier, Philip J. Woest, P. B. Schechter. 290-299
- Architectural Tradeoffs in the Design of MIPS-XPaul Chow, Mark Horowitz. 300-308
- The Hardware Architecture of the CRISP MicroprocessorDavid R. Ditzel, Hubert R. McLellan, Alan D. Berenbaum. 309-319