Sriram Vajapeyam - researchr alias

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Viewing Publication 1 - 16 from 16

2002

Page-Level Behavior of Cache ContentionSiddhartha V. Tambat, Sriram Vajapeyam. cal, 1, 2002. [doi]

2001

Early 21st Century Processors - Guest Editors IntroductionSriram Vajapeyam, Mateo Valero. Computer, 34(4):47-50, 2001. [doi]

2000

Non-Strict Cache Coherence: Exploiting Data-Race Tolerance in Emerging ApplicationsSiddhartha V. Tambat, Sriram Vajapeyam. icpp 2000: 87-94 [doi]

1999

Whither Indian Computer Science R & D?Sriram Vajapeyam. hipc 1999: 175

Dynamic Vectorization: A Mechanism for Exploiting Far-Flung ILP in Ordinary ProgramsSriram Vajapeyam, P. J. Joseph, Tulika Mitra. isca 1999: 16-27 [doi]

1998

Load Balancing in a Heterogeneous Computing EnvironmentSridhar Gopal, Sriram Vajapeyam. hicss 1998: 796 [doi]

Instruction Issue Logic for High-Performance, Interruptable Pipelined ProcessorsGurindar S. Sohi, Sriram Vajapeyam. isca 1998: 329-336 [doi]

1997

Trace Processors: Moving to Fourth-Generation MicroarchitecturesJames E. Smith, Sriram Vajapeyam. Computer, 30(9):68-74, 1997.

Improving Superscalar Instruction Dispatch and Issue by Exploiting Dynamic Code SequencesSriram Vajapeyam, Tulika Mitra. isca 1997: 1-12 [doi]

1996

Program-level control of network delay for parallel asynchronous iterative applicationsP. J. Joseph, Sriram Vajapeyam. hipc 1996: 88-93 [doi]

1993

Toward Effective Scalar Hardware for Highly Vectorizable ApplicationsSriram Vajapeyam, Wei-Chung Hsu. jpdc, 19(3):147-162, 1993.

1992

On the instruction-level characteristics of scalar code in highly-vectorized scientific applicationsSriram Vajapeyam, Wei-Chung Hsu. euromicro 1992: 20-28 [doi]

1991

An Empirical Study of the CRAY Y-MP Processor Using the Perfect Club BenchmarksSriram Vajapeyam, Gurindar S. Sohi, Wei-Chung Hsu. isca 1991: 170-179 [doi]

1990

Exploitation of operation-level parallelism in a processor of the CRAY X-MPSriram Vajapeyam, Gurindar S. Sohi, Wei-Chung Hsu. iccd 1990: 20-23 [doi]

1989

Tradeoffs in Instruction Format Design for Horizontal ArchitecturesGurindar S. Sohi, Sriram Vajapeyam. asplos 1989: 15-25

1987

Instruction Issue Logic for High-Performance, Interruptable Pipelined ProcessorsGurindar S. Sohi, Sriram Vajapeyam. isca 1987: 27-34

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