Abstract is missing.
- Improving Superscalar Instruction Dispatch and Issue by Exploiting Dynamic Code SequencesSriram Vajapeyam, Tulika Mitra. 1-12 [doi]
- Exploiting Instruction Level Parallelism in Processors by Caching Scheduled GroupsRavi Nair, Martin E. Hopkins. 13-25 [doi]
- DAISY: Dynamic Compilation for 100 Architectural CompatibilityKemal Ebcioglu, Erik R. Altman. 26-37 [doi]
- On Deadlocks in Interconnection NetworksTimothy Mark Pinkston, Sugath Warnakulasuriya. 38-49 [doi]
- Implementing Multidestination Worms in Switch-Based Parallel Systems: Architectural Alternatives and their ImpactCraig B. Stunkel, Rajeev Sivaram, Dhabaleswar K. Panda. 50-61 [doi]
- Tolerating Multiple Failures in RAID Architectures with Optimal Storage and Uniform DeclusteringGuillermo A. Alvarez, Walter A. Burkhard, Flaviu Cristian. 62-72 [doi]
- Hardware Fault Containment in Scalable Shared-Memory MultiprocessorsDan Teodosiu, Joel Baxter, Kinshuk Govil, John Chapin, Mendel Rosenblum, Mark Horowitz. 73-84 [doi]
- Effects of Communication Latency, Overhead, and Bandwidth in a Cluster ArchitectureRichard P. Martin, Amin Vahdat, David E. Culler, Thomas E. Anderson. 85-97 [doi]
- The Mercury Interconnect Architecture: A Cost-effective Infrastructure for High-performance ServersWolf-Dietrich Weber, Stephen Gold, Pat Helland, Takeshi Shimizu, Thomas Wicki, Winfried W. Wilcke. 98-107 [doi]
- The Design and Analysis of a Cache Architecture for Texture MappingZiyad S. Hakura, Anoop Gupta. 108-120 [doi]
- Designing High Bandwidth On-Chip CachesKenneth M. Wilson, Kunle Olukotun. 121-132 [doi]
- Memory-System Design Considerations for Dynamically-Scheduled ProcessorsKeith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic. 133-143 [doi]
- The Interaction of Software Prefetching with ILP Processors in Shared-Memory SystemsParthasarathy Ranganathan, Vijay S. Pai, Hazim Abdel-Shafi, Sarita V. Adve. 144-156 [doi]
- VM-Based Shared Memory on Low-Latency, Remote-Memory-Access NetworksLeonidas I. Kontothanassis, Galen C. Hunt, Robert Stets, Nikos Hardavellas, Michal Cierniak, Srinivasan Parthasarathy, Wagner Meira Jr., Sandhya Dwarkadas, Michael L. Scott. 157-169 [doi]
- Efficient Synchronization: Let Them Eat QOLBAlain Kägi, Doug Burger, James R. Goodman. 170-180 [doi]
- Dynamic Speculation and Synchronization of Data DependencesAndreas Moshovos, Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi. 181-193 [doi]
- Dynamic Instruction ReuseAvinash Sodani, Gurindar S. Sohi. 194-205 [doi]
- Complexity-Effective Superscalar ProcessorsSubbarao Palacharla, Norman P. Jouppi, James E. Smith. 206-218 [doi]
- Coherence Controller Architectures for SMP-Based CC-NUMA MultiprocessorsMaged M. Michael, Ashwini K. Nanda, Beng-Hong Lim, Michael L. Scott. 219-228 [doi]
- Reactive NUMA: A Design for Unifying S-COMA and CC-NUMABabak Falsafi, David A. Wood. 229-240 [doi]
- The SGI Origin: A ccNUMA Highly Scalable ServerJames Laudon, Daniel Lenoski. 241-251 [doi]
- Prefetching Using Markov PredictorsDoug Joseph, Dirk Grunwald. 252-263 [doi]
- Data Prefetching on the HP PA-8000Vatsa Santhanam, Edward H. Gornish, Wei-Chung Hsu. 264-273 [doi]
- Target Prediction for Indirect JumpsPo-Yung Chang, Eric Hao, Yale N. Patt. 274-283 [doi]
- The Agree Predictor: A Mechanism for Reducing Negative Branch History InterferenceEric Sprangle, Robert S. Chappell, Mitch Alsup, Yale N. Patt. 284-291 [doi]
- Trading Conflict and Capacity Aliasing in Conditional Branch PredictorsPierre Michaud, André Seznec, Richard Uhlig. 292-303 [doi]
- A Language for Describing Predictors and Its Application to Automatic SynthesisJoel S. Emer, Nicholas C. Gloy. 304-314 [doi]
- The Energy Efficiency of IRAM ArchitecturesRichard Fromm, Stylianos Perissakis, Neal Cardwell, Christoforos E. Kozyrakis, Bruce McGaughy, David A. Patterson, Thomas E. Anderson, Katherine A. Yelick. 327-337 [doi]
- DataScalar ArchitecturesDoug Burger, Stefanos Kaxiras, James R. Goodman. 338-349 [doi]