James R. Goodman - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 49 from 49

2014

Author retrospective for code scheduling and register allocation in large basic blocksJames R. Goodman, Wei-Chung Hsu. ics 2014: 4-5 [doi]

2011

Transactional conflict decoupling and value predictionFuad Tabba, Andrew W. Hay, James R. Goodman. ics 2011: 33-42 [doi]

2009

NZTM: nonblocking zero-indirection transactional memoryFuad Tabba, Mark Moir, James R. Goodman, Andrew W. Hay, Cong Wang. spaa 2009: 204-213 [doi]

2004

Billion-Transistor Architectures: There and Back AgainDoug Burger, James R. Goodman. Computer, 37(3):22-28, 2004. [doi]

Inferential Queueing and Speculative PushRavi Rajwar, Alain Kägi, James R. Goodman. ijpp, 32(3):225-258, 2004. [doi]

Computerarchitektur - Strukturen, Konzepte, Grundlagen (4. Aufl.)Andrew S. Tanenbaum, James R. Goodman. Pearson Studium, 2004. [doi]

2003

Inferential queueing and speculative push for reducing critical communication latenciesRavi Rajwar, Alain Kägi, James R. Goodman. ics 2003: 273-284 [doi]

2002

Transactional lock-free execution of lock-based programsRavi Rajwar, James R. Goodman. asplos 2002: 5-17 [doi]

2001

Speculative lock elision: enabling highly concurrent multithreaded executionRavi Rajwar, James R. Goodman. euromicro 2001: 294-305 [doi]

Computerarchitektur - Strukturen, Konzepte, Grundlagen (4. Aufl.)Andrew S. Tanenbaum, James R. Goodman. Pearson Studium, 2001.

2000

Improving the Throughput of Synchronization by Insertion of DelaysRavi Rajwar, Alain Kägi, James R. Goodman. hpca 2000: 168 [doi]

1999

Improving CC-NUMA Performance Using Instruction-Based PredictionStefanos Kaxiras, James R. Goodman. hpca 1999: 161 [doi]

DataScalar: A memory-centric approach to computingStefanos Kaxiras, Doug Burger, James R. Goodman. jsa, 45(12-13):1001-1022, 1999. [doi]

1998

Retrospective: Using Cache Memory to Reduce Processor-Memory TrafficJames R. Goodman. isca 1998: 32-33 [doi]

Using Cache Memory to Reduce Processor-Memory TrafficJames R. Goodman. isca 1998: 255-262 [doi]

A Study of Three Dynamic Approaches to Handle Widely Shared Data in Shared-memory MultiprocessorsStefanos Kaxiras, Stein Gjessing, James R. Goodman. ics 1998: 457-464 [doi]

1997

Billion-Transistor Architectures - Guest Editors IntroductionDoug Burger, James R. Goodman. Computer, 30(9):46-49, 1997.

Memory SystemsDoug Burger, James R. Goodman, Gurindar S. Sohi. In Allen B. Tucker, editor, The Computer Science and Engineering Handbook. pages 447-461, CRC Press, 1997.

DataScalar ArchitecturesDoug Burger, Stefanos Kaxiras, James R. Goodman. isca 1997: 338-349 [doi]

Limited bandwidth to affect processor designDoug Burger, James R. Goodman, Alain Kägi. micro, 17(6):55-62, 1997. [doi]

Efficient Synchronization: Let Them Eat QOLBAlain Kägi, Doug Burger, James R. Goodman. isca 1997: 170-180 [doi]

1996

Memory Bandwidth Limitations of Future MicroprocessorsDoug Burger, James R. Goodman, Alain Kägi. isca 1996: 78-89 [doi]

The GLOW Cache Coherence Protocol Extensions for Widely Shared DataStefanos Kaxiras, James R. Goodman. ics 1996: 35-43 [doi]

1995

Techniques for Reducing Overheads of Shared-Memory MultiprocessingAlain Kägi, Nagi Aboulenein, Doug Burger, James R. Goodman. ics 1995: 11-20 [doi]

1994

Hardware Support for Synchronization in the Scalable Coherent Interface (SCI)Nagi Aboulenein, James R. Goodman, Stein Gjessing, Philip J. Woest. ipps 1994: 141-150

The Impact of Pipelined Channels on k-ary n-Cube NetworksSteven L. Scott, James R. Goodman. tpds, 5(1):2-16, 1994. [doi]

1993

Performance of Pruning-Cache Directories for Large-Scale MultiprocessorsSteven L. Scott, James R. Goodman. tpds, 4(5):520-534, 1993. [doi]

1992

1989

Efficent Synchronization Primitives for Large-Scale Cache-Coherent MultiprocessorsJames R. Goodman, Mary K. Vernon, Philip J. Woest. asplos 1989: 64-75

On the Minimization of Loads/Stores in Local Register AllocationWei-Chung Hsu, Charles N. Fischer, James R. Goodman. TSE, 15(10):1252-1260, 1989. [doi]

Restricted Fetch&Phi operations for parallel processingGurindar S. Sohi, James E. Smith, James R. Goodman. ics 1989: 410-416 [doi]

1988

The Wisconsin Multicube: A New Large-Scale Cache-Coherent MultiprocessorJames R. Goodman, Philip J. Woest. isca 1988: 422-431

Reply to David R. Cheriton's, Pat Boyle's, and Gert A. Slavenburg's "Comments on 'Coherency for multiprocessor virtual addressed caches' by James R. Goodman"James R. Goodman. sigarch, 16(3):7, 1988. [doi]

Code scheduling and register allocation in large basic blocksJames R. Goodman, Wei-Chung Hsu. ics 1988: 442-452 [doi]

1987

Coherency for Multiprocessor Virtual Address CachesJames R. Goodman. asplos 1987: 72-81

WISQ: A Restartable Architecture Using QueuesAndrew R. Pleszkun, James R. Goodman, Wei-Chung Hsu, R. T. Joersz, George E. Bier, Philip J. Woest, P. B. Schechter. isca 1987: 290-299

1986

Comments on A Massive Memory Machine James R. Goodman, Honesty C. Young. TC, 35(10):907-910, 1986.

On the Use of Registers vs. Cache to Minimize Memory TrafficJames R. Goodman, Wei-Chung Hsu. isca 1986: 375-383

The Design of a Queue-Based Vector SupercomputerHonesty C. Young, James R. Goodman. icpp 1986: 483-486

1985

PIPE: A VLSI Decoupled ArchitectureJames R. Goodman, Jian-tu Hsieh, Koujuch Liou, Andrew R. Pleszkun, P. B. Schechter, Honesty C. Young. isca 1985: 20-27

Instruction Cache Replacement Policies and OrganizationsJames E. Smith, James R. Goodman. TC, 34(3):234-241, 1985.

1984

The Use of Static Column RAM as a Memory HierarchyJames R. Goodman, MenChow Chiang. isca 1984: 167-174

1983

Using Cache Memory to Reduce Processor-Memory TrafficJames R. Goodman. isca 1983: 124-131

A Study of Instruction Cache Organizations and Replacement PoliciesJames E. Smith, James R. Goodman. isca 1983: 132-137

1982

VLSI Considerations that Influence Data Flow ArchitectureChinya V. Ravishankar, James R. Goodman. compcon 1982: 228-232

1981

Hypertree: A Multiprocessor Interconnection TopologyJames R. Goodman, Carlo H. Séquin. TC, 30(12):923-933, 1981.

1972

Some Properties of Iterative Square-Rooting Methods Using High-Speed MultiplicationChitoor V. Ramamoorthy, James R. Goodman, K. H. Kim. TC, 21(8):837-847, 1972. [doi]

Sign in or sign up to see more results.

runs on WebDSL