Abstract is missing.
- A Vector and Array Multiprocessor Extension of the Sylvan ArchitectureForbes J. Burkowski. 4-11
- The Pringle Parallel ComputerAlejandro A. Kapauan, J. Timothy Field, Dennis Gannon, Lawrence Snyder. 12-20
- A State-of-the-Art SIMD Two-Dimensional FFT Array ProcessorMehrad Yasrebi, G. Jack Lipovski. 21-27
- A Generalized Object Display Processor ArchitectureSamuel M. Goldwasser. 38-47
- A Special Purpose LSI Processor Using the DDA Algorithm for Image TransformationKatsura Kawakami, Shigeo Shimazaki. 48-54
- The Status of MANIP-A Multicomputer Architecture for Solving Combinatorial Extremum-Search ProblemsBenjamin W. Wah, Guo-Jie Li, Chee Fen Yu. 56-63
- The Schuss Filter: A Processor for Non-Numerical Data ProcessingRubén González-Rubio, J. Rohmer, D. Terral. 64-73
- The Design and Implementation of a VLSI Chess Move GeneratorCarl Ebeling, Andrew J. Palay. 74-80
- Performance Analysis of Circuit Switching Baseline Interconnection NetworksManjai Lee, Chuan-lin Wu. 82-90
- The Importance of Being SquareClyde P. Kruskal, Marc Snir. 91-98
- Instruction Issue Logic for Pipelined SupercomputersShlomo Weiss, James E. Smith. 110-118
- The Reduction of Branch Instruction Execution Overhead Using Structured Control FlowRobert G. Wedig, Marc A. Rose. 119-125
- Fast Execution of Loops With IF StatementsUtpal Banerjee, Daniel Gajski. 126-132
- A Parallel Pipelined Relational Query Processor: An Architectural OverviewDaniel Gajski, Won Kim, Shinya Fushimi. 134-141
- An Efficient VLSI Dictionary MachineArun K. Somani, Vinod K. Agarwal. 142-150
- Dictionary Machines With a Small Number of ProcessorsAllan L. Fisher. 151-156
- Experimental Evaluation of On-Chip Microprocessor Cache MemoriesMark D. Hill, Alan Jay Smith. 158-166
- The Use of Static Column RAM as a Memory HierarchyJames R. Goodman, MenChow Chiang. 167-174
- The Design of an Object Oriented ArchitectureYutaka Ishikawa, Mario Tokoro. 178-187
- Architecture of SOAR: Smalltalk on a RISCDavid Ungar, Ricki Blau, Peter Foley, A. Dain Samples, David A. Patterson. 188-197
- Design of Instruction Set Architectures for Support of High-Level Languages Pradip Bose, Edward S. Davidson. 198-206
- Automatic Synthesis of Systolic Arrays from Uniform Recurrent EquationsPatrice Quinton. 208-214
- Multi-Dimensional Systolic Networks for Discrete Fourier TransformChang-Nian Zhang, David Y. Y. Yun. 215-222
- Data Broadcasting in Linearly Scheduled Array ProcessorsJosé A. B. Fortes, Dan I. Moldovan. 224-231
- Modular Matrix Multiplication on a Linear ArrayI. V. Ramakrishnan, Peter J. Varman. 232-238
- Joint Encryption and Error Correction SchemesT. R. N. Rao. 240-241
- Unidirectional Error Correction/Detection for VLSI MemoryBella Bose. 242-244
- Error-Correcting Codes for Semiconductor MemoriesC. L. Chen. 245-247
- Soft Error Correction for Increased Densities in VLSI MemoriesKhaled A. S. Abdel-Ghaffar, Robert J. McEliece. 248-250
- Combining Speed with Alpha-Particle Induced Memory Error Tolerance in a Large Boolean Vector Machine (Extended Abstract)Richard M. King, Robert A. Wagner. 251-253
- On the Performance of Loosely Coupled MultiprocessorsLaxmi N. Bhuyan. 256-262
- Scheduling of Tasks for Distributed ProcessorsRavi Mehrotra, Sarosh Talukdar. 263-270
- Message Repository Definitional Facility: An Architectural Model for Interprocess CommunicationKrishna M. Kavi, Edward W. Banios. 271-278
- Fault-Secure Algorithms for Multiple-Processor SystemsPrithviraj Banerjee, Jacob A. Abraham. 279-287
- Execution of Logic Programs on a Dataflow ArchitectureLubomir Bic. 290-296
- A High Performance Factoring MachineWalter G. Rudd, Duncan A. Buell, Donald M. Chiarulli. 297-300
- A Characterization of Processor Performance in the VAX-11/780Joel S. Emer, Douglas W. Clark. 301-310
- The Peripheral Processor PP4 - A Highly Regular VLSI ProcessorWolf-Dietrich Moeller, Gerd Sandweg. 312-318
- VLSI Based Design Principles for MIMD Multiprocessor Computers with Distributed Memory ManagementLars Philipson. 319-327
- Dhiraj K. Pradhan: A Multiprocessor Network Suitable for Single-Chip VLSI ImplementationMaheswara R. Samatham. 328-337
- Dynamic Decentralized Cache Schemes for MIMD Parallel ProcessorsLarry Rudolph, Zary Segall. 340-347
- A Low-Overhead Coherence Solution for Multiprocessors with Private Cache MemoriesMark S. Papamarcos, Janak H. Patel. 348-354
- An Economical Solution to the Cache Coherence ProblemJames K. Archibald, Jean-Loup Baer. 355-362
- Cache Hit Ratios With Geometric Task Switch IntervalsIlkka J. Haikala. 364-371