Abstract is missing.
- Impact of Chip-Level Integration on Performance of OLTP WorkloadsLuiz André Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Ben Verghese. 3-14 [doi]
- Toward a Cost-Effective DSM Organization That Exploits Processor-Memory IntegrationJosep Torrellas, Liuxi Yang, Anthony-Trung Nguyen. 15-25 [doi]
- Impact of Heterogeneity on DSM PerformanceRenato J. O. Figueiredo, José A. B. Fortes. 26 [doi]
- Design of a Parallel Vector Access Unit for SDRAM Memory SystemsBinu K. Mathew, Sally A. McKee, John B. Carter, Al Davis. 39-48 [doi]
- Modified LRU Policies for Improving Second-Level Cache BehaviorWayne A. Wong, Jean-Loup Baer. 49-60 [doi]
- eXtended Block CacheStéphan Jourdan, Lihu Rappoport, Yoav Almog, Mattan Erez, Adi Yoaz, Ronny Ronen. 61 [doi]
- Flit-Reservation Flow ControlLi-Shiuan Peh, William J. Dally. 73-84 [doi]
- Performance Evaluation of Dynamic Reconfiguration in High-Speed Local Area NetworksRafael Casado, Aurelio Bermúdez, Francisco J. Quiles, José L. Sánchez, José Duato. 85-96 [doi]
- Investigating QoS Support for Traffic Mixes with the MediaWorm RouterKi Hwan Yum, Aniruddha S. Vaidya, Chita R. Das, Anand Sivasubramaniam. 97 [doi]
- Quantifying the SMT Layout Overhead-Does SMT Pull Its Weight?James Burns, Jean-Luc Gaudiot. 109-120 [doi]
- Software-Controlled Multithreading Using Informing Memory OperationsTodd C. Mowry, Sherwyn R. Ramkissoon. 121-132 [doi]
- Dynamic Cluster Assignment MechanismsRamon Canal, Joan-Manuel Parcerisa, Antonio González. 133 [doi]
- High-Throughput Coherence ControllersAshwini K. Nanda, Anthony-Trung Nguyen, Maged M. Michael, Douglas J. Joseph. 145-155 [doi]
- Coherence Communication Prediction in Shared-Memory MultiprocessorsStefanos Kaxiras, Cliff Young. 156-167 [doi]
- Improving the Throughput of Synchronization by Insertion of DelaysRavi Rajwar, Alain Kägi, James R. Goodman. 168 [doi]
- On the Performance of Hand vs. Automatically Optimized Numerical CodesMarta Jiménez, José M. Llabería, Agustin Fernández. 183-194 [doi]
- Cache-Efficient Matrix TranspositionSiddhartha Chatterjee, Sandeep Sen. 195-205 [doi]
- A Prefetching Technique for Irregular Accesses to Linked Data StructuresMagnus Karlsson, Fredrik Dahlgren, Per Stenström. 206-217 [doi]
- Reducing Code Size with Run-Time DecompressionCharles Lefurgy, Eva Piccininni, Trevor N. Mudge. 218 [doi]
- Decoupled Value Prediction on Trace ProcessorsSang-Jeong Lee, Yuan Wang, Pen-Chung Yew. 231-240 [doi]
- Branch Transition Rate: A New Metric for Improved Branch Classification AnalysisMichael Haungs, Phil Sallee, Matthew K. Farrens. 241-250 [doi]
- Combining Static and Dynamic Branch Prediction to Reduce Destructive AliasingHarish Patil, Joel S. Emer. 251 [doi]
- The Effect of Network Total Order, Broadcast, and Remote-Write Capability on Network-Based Shared Memory ComputingRobert Stets, Sandhya Dwarkadas, Leonidas I. Kontothanassis, Umit Rencuzogullari, Michael L. Scott. 265-276 [doi]
- PowerMANNA: A Parallel Architecture Based on the PowerPC MPC620Peter M. Behr, S. Pletner, Angela C. Sodan. 277-286 [doi]
- A DSM Architecture for a Parallel Computer Cenju-4Takeo Hosomi, Yasushi Kanoh, Masaaki Nakamura, Tetsuya Hirose. 287 [doi]
- A Technique for High Bandwidth and Deterministic Low Latency Load/Store Accesses to Multiple Cache BanksHenk Neefs, Hans Vandierendonck, Koenraad De Bosschere. 313-324 [doi]
- Trace Cache Redundancy: Red & Blue TracesAlex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero. 325 [doi]
- Investigating the Performance of Two Programming Models for Clusters of SMP PCsFranck Cappello, Olivier Richard, Daniel Etiemble. 349-359 [doi]
- Performance Analysis and Visualization of Parallel Systems Using SimOS and Rivet: A Case StudyRobert Bosch, Chris Stolte, Gordon Stoll, Mendel Rosenblum, Pat Hanrahan. 360 [doi]
- Register Organization for Media ProcessingScott Rixner, William J. Dally, Brucek Khailany, Peter R. Mattson, Ujval J. Kapasi, John D. Owens. 375-386 [doi]
- Architectural Issues in Java Runtime SystemsRamesh Radhakrishnan, Narayanan Vijaykrishnan, Lizy Kurian John, Anand Sivasubramaniam. 387-398 [doi]
- The Best Distribution for a Parallel OpenGL 3D Engine with Texture CachesAlexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam. 399-408 [doi]
- Cache Memory Design for Network ProcessorsTzi-cker Chiueh, Prashant Pradhan. 409 [doi]