Abstract is missing.
- Fifty years of microarchitectureHarvey G. Cragon, Ernest Cockrell Jr.. 2 [doi]
- Skipper: a microarchitecture for exploiting control-flow independenceChen-Yong Cher, T. N. Vijaykumar. 4-15 [doi]
- Performance characterization of a hardware mechanism for dynamic optimizationBrian Fahs, Satarupa Bose, Matthew M. Crum, Brian Slechta, Francesco Spadini, Tony Tung, Sanjay J. Patel, Steven S. Lumetta. 16-27 [doi]
- Using variable-MHz microprocessors to efficiently handle uncertainty in real-time systemsEric Rotenberg. 28-39 [doi]
- A design space evaluation of grid processor architecturesRamadass Nagarajan, Karthikeyan Sankaralingam, Doug Burger, Stephen W. Keckler. 40-51 [doi]
- Reducing set-associative cache energy via way-prediction and selective direct-mappingMichael D. Powell, Amit Agarwal, T. N. Vijaykumar, Babak Falsafi, Kaushik Roy. 54-65 [doi]
- A code decompression architecture for VLIW processorsYuan Xie, Wayne Wolf, Haris Lekatsas. 66-75 [doi]
- Direct load: dependence-linked dataflow resolution of load address and cache coordinateByung-Kwon Chung, Jinsuo Zhang, Jih-Kwon Peir, Shih-Chang Lai, Konrad Lai. 76-87 [doi]
- Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resourcesDmitry Ponomarev, Gurhan Kucuk, Kanad Ghose. 90-101 [doi]
- Exploiting VLIW schedule slacks for dynamic and leakage energy reductionWei Zhang 0002, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, David Duarte, Yuh-Fang Tsai. 102-113 [doi]
- Reducing power with dynamic critical path informationJohn S. Seng, Eric Tune, Dean M. Tullsen. 114-123 [doi]
- Direct addressed caches for reduced power consumptionEmmett Witchel, Samuel Larsen, C. Scott Ananian, Krste Asanovic. 124-133 [doi]
- Emerging applications for the connected homeAndrew Wolfe. 136 [doi]
- Modulo schedule buffersMatthew C. Merten, Wen-mei W. Hwu. 138-149 [doi]
- Graph-partitioning based instruction scheduling for clustered processorsAlex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González. 150-159 [doi]
- Modulo scheduling with integrated register spilling for clustered VLIW architecturesJavier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero. 160-169 [doi]
- Efficient static single assignment form for predicationArtour Stoutchinin, François de Ferrière. 172-181 [doi]
- The impact of if-conversion and branch prediction on program execution on the Intel Itanium processorYoungsoo Choi, Allan D. Knies, Luke Gerke, Tin-Fook Ngai. 182-191 [doi]
- Mapping reference code to irregular DSPs within the retargetable, optimizing compiler COGEN(T)Gary William Grewal, Thomas Charles Wilson. 192-202 [doi]
- Select-free instruction scheduling logicMary D. Brown, Jared Stark, Yale N. Patt. 204-213 [doi]
- Dual use of superscalar datapath for transient-fault detection and recoveryJoydeep Ray, James C. Hoe, Babak Falsafi. 214-224 [doi]
- A high-speed dynamic instruction scheduling scheme for superscalar processorsMasahiro Goshima, Kengo Nishino, Toshiaki Kitamura, Yasuhiko Nakashima, Shinji Tomita, Shin-ichiro Mori. 225-236 [doi]
- Reducing the complexity of the register file in dynamic superscalar processorsRajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi. 237-248 [doi]
- Saving energy with architectural and frequency adaptations for multimedia applicationsChristopher J. Hughes, Jayanth Srinivasan, Sarita V. Adve. 250-261 [doi]
- Enhancing loop buffering of media and telecommunications applications using low-overhead predicationJohn W. Sias, Hillery C. Hunter, Wen-mei W. Hwu. 262-273 [doi]
- Cool-cache for hot multimediaOsman S. Unsal, Raksit Ashok, Israel Koren, C. Mani Krishna, Csaba Andras Moritz. 274-283 [doi]
- ZR: a 3D API transparent technology for chunk renderingEmile Hsieh, Vladimir Pentkovski, Thomas Piazza. 284-291 [doi]
- Speculative lock elision: enabling highly concurrent multithreaded executionRavi Rajwar, James R. Goodman. 294-305 [doi]
- Dynamic speculative precomputationJamison D. Collins, Dean M. Tullsen, Hong Wang 0003, John Paul Shen. 306-317 [doi]
- Handling long-latency loads in a simultaneous multithreading processorDean M. Tullsen, Jeffery A. Brown. 318-327 [doi]
- Correctly implementing value prediction in microprocessors that support multithreading or multiprocessingMilo M. K. Martin, Daniel J. Sorin, Harold W. Cain, Mark D. Hill, Mikko H. Lipasti. 328-337 [doi]