Wei Zhang 0002 - researchr alias

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Viewing Publication 1 - 75 from 75

2021

Cache Leakage Reduction Techniques for Hybrid SPM-Cache ArchitecturesHao Wen, Wei Zhang 0002. jcsc, 30(1), 2021. [doi]

2020

Denial of Service in CPU-GPU Heterogeneous ArchitecturesHao Wen, Wei Zhang 0002. hpec 2020: 1-5 [doi]

2019

Cracking Randomized Coalescing Techniques with An Efficient Profiling-Based Side-Channel Attack to GPUXin Wang 0056, Wei Zhang 0002. isca 2019: [doi]

Heterogeneous Cache Hierarchy Management for Integrated CPU-GPU ArchitectureHao Wen, Wei Zhang 0002. hpec 2019: 1-6 [doi]

2018

2017

Static WCET Analysis of GPUs with Predictable Warp SchedulingYijie Huangfu, Wei Zhang 0002. isorc 2017: 101-108 [doi]

2015

Exploiting Static Non-Uniform Cache Architectures for Hard Real-Time ComputingYiqiang Ding, Wei Zhang 0002. jcse, 9(4), 2015. [doi]

Leveraging Hotspots and Improving Chip Reliability via Carbon Nanotube Grid Thermal StructureHao Liang, Wei Zhang 0002, Jiale Huang, Shengqi Yang, Pallav Gupta. tvlsi, 23(4):731-742, 2015. [doi]

Scratchpad Memory Architectures and Allocation Algorithms for Hard Real-Time Multicore ProcessorsYu Liu, Wei Zhang 0002. jcse, 9(2), 2015. [doi]

2014

Exploiting Standard Deviation of CPI to Evaluate Architectural Time-PredictabilityWei Zhang 0002, Yiqiang Ding. jcse, 8(1):34-42, 2014. [doi]

Hop-Based Priority Scheduling to Improve Worst-Case Inter-core Communication LatencyYiqiang Ding, Wei Zhang 0002. euc 2014: 52-57 [doi]

Bounding the Worst-Case Execution Time of Static NUCA CachesYiqiang Ding, Wei Zhang 0002. hpcc 2014: 1181-1184 [doi]

Two-Level Scratchpad Memory Architectures to Achieve Time Predictability and High PerformanceYu Liu, Wei Zhang 0002. jcse, 8(4):215-227, 2014. [doi]

Performance Implication of Multicore Cache Locking on General-Purpose ProcessorsMatthew Loach, Wei Zhang 0002. hpcc 2014: 328-331 [doi]

Characterizing Energy Consumption of Real-Time and Media Benchmarks on Hybrid SPM-CachesLan Wu, Yiqiang Ding, Wei Zhang 0002. hpcc 2014: 526-533 [doi]

Comparing Separate and Statically-Partitioned Caches for Time-Predictable Multicore ProcessorsLan Wu, Yiqiang Ding, Wei Zhang 0002. jcse, 8(1):25-33, 2014. [doi]

2013

Standard deviation of CPI: A new metric to evaluate architectural time predictabilityWei Zhang 0002, Yiqiang Ding. asap 2013: 111-112 [doi]

Hybrid SPM-cache architectures to achieve high time predictability and performanceWei Zhang 0002, Yiqiang Ding. asap 2013: 297-304 [doi]

On the interactions between real-time scheduling and inter-thread cached interferences for multicore processorsYiqiang Ding, Wei Zhang 0002. isqed 2013: 627-634 [doi]

Multicore Real-Time Scheduling to Reduce Inter-Thread Cache InterferencesYiqiang Ding, Wei Zhang 0002. jcse, 7(1):67-80, 2013. [doi]

Counter-Based Approaches for Efficient WCET Analysis of Multicore Processors with Shared CachesYiqiang Ding, Wei Zhang 0002. jcse, 7(4):285-299, 2013. [doi]

Bounding Worst-Case DRAM Performance on Multicore ProcessorsYiqiang Ding, Lan Wu, Wei Zhang 0002. jcse, 7(1):53-66, 2013. [doi]

Static worst-case lifetime estimation of wireless sensor networks: A case study on VigilNetYu Liu, Wei Zhang 0002. jsa, 59(4-5):224-233, 2013. [doi]

Reducing worst-case execution time of hybrid SPM-cachesLan Wu, Wei Zhang 0002. ipccc 2013: 1-9 [doi]

2012

Static Timing Analysis of Shared Caches for Multicore ProcessorsWei Zhang 0002, Jun Yan. jcse, 6(4):267-278, 2012. [doi]

Time-Predictable Java Dynamic Compilation on Multicore ProcessorsYu Sun 0006, Wei Zhang 0002. jcse, 6(1):26-38, 2012. [doi]

On-line Trace Based Automatic Parallelization of Java Programs on Multicore PlatformsYu Sun 0006, Wei Zhang 0002. jcse, 6(2):105-118, 2012. [doi]

Architectural time-predictability factor (ATF): a metric to evaluate time predictability of processorsYiqiang Ding, Wei Zhang 0002. sigbed, 9(4):6-15, 2012. [doi]

Multicore-Aware Code Co-Positioning to Reduce WCET on Dual-Core Processors with Shared Instruction CachesYiqiang Ding, Wei Zhang 0002. jcse, 6(1):12-25, 2012. [doi]

Exploiting SPM-aware Scheduling on EPIC architectures for high-performance real-time systemsYu Liu, Wei Zhang 0002. hpec 2012: 1-2 [doi]

Exploiting multi-level scratchpad memories for time-predictable multicore computingYu Liu, Wei Zhang 0002. iccd 2012: 61-66 [doi]

A Model Checking Based Approach to Bounding Worst-Case Execution Time for Multicore ProcessorsLan Wu, Wei Zhang 0002. tecs, 11(S2):56, 2012. [doi]

2011

2010

Replica victim caching to improve cache reliability against transient errorsWei Zhang 0002. ijhpsa, 2(3/4):229-239, 2010. [doi]

A time-predictable dual-core prototype on FPGASatya Mohan Raju Gudidevuni, Wei Zhang 0002. ACMse 2010: 7 [doi]

2009

Improving Java performance and energy dissipation through efficient code cachingYu Sun 0006, Wei Zhang 0002. dafes, 13(3):179-192, 2009. [doi]

2007

Reducing branch predictor leakage energy by exploiting loopsWei Zhang 0002, Bramha Allu. tecs, 6(2):11, 2007. [doi]

Real-time Accurate Object Detection using Multiple ResolutionsWei Zhang 0002, Gregory J. Zelinsky, Dimitris Samaras. iccv 2007: 1-8 [doi]

2006

Reducing dynamic and leakage energy in VLIW architecturesWei Zhang 0002, Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. tecs, 5(1):1-28, 2006. [doi]

Reducing Instruction Translation Look-Aside Buffer Energy Through Compiler-Directed ResizingBramha Allu, Wei Zhang 0002. jolpe, 2(2):140-147, 2006. [doi]

2005

Computing Cache Vulnerability to Transient Errors and Its ImplicationWei Zhang 0002. dft 2005: 427-435 [doi]

Reducing data cache leakage energy using a compiler-based approachWei Zhang 0002, Mahmut T. Kandemir, Mustafa Karaköy, Guangyu Chen. tecs, 4(3):652-678, 2005. [doi]

Object Class Recognition Using Multiple Layer Boosting with Heterogeneous FeaturesWei Zhang 0002, Bing Yu, Gregory J. Zelinsky, Dimitris Samaras. cvpr 2005: 323-330 [doi]

A Computational Model of Eye Movements during Object Class DetectionWei Zhang 0002, Hyejin Yang, Dimitris Samaras, Gregory J. Zelinsky. nips 2005: 1609-1616 [doi]

Exploiting the replication cache to improve performance for multiple-issue microprocessorsBramha Allu, Wei Zhang 0002. sigarch, 33(3):63-71, 2005. [doi]

The Role of Top-down and Bottom-up Processes in Guiding Eye Movements during Visual SearchGregory J. Zelinsky, Wei Zhang 0002, Bing Yu, Xin Chen, Dimitris Samaras. nips 2005: 1569-1576 [doi]

2004

2003

Interprocedural optimizations for improving data cache performance of array-intensive embedded applicationsWei Zhang 0002, Guangyu Chen, Mahmut T. Kandemir, Mustafa Karaköy. dac 2003: 887-892 [doi]

A compiler approach for reducing data cache energyWei Zhang 0002, Mustafa Karaköy, Mahmut T. Kandemir, Guangyu Chen. ics 2003: 76-85 [doi]

Performance, energy, and reliability tradeoffs in replicating hot cache linesWei Zhang 0002, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin. cases 2003: 309-317 [doi]

ICR: In-Cache Replication for Enhancing Data Cache ReliabilityWei Zhang 0002, Sudhanva Gurumurthi, Mahmut T. Kandemir, Anand Sivasubramaniam. dsn 2003: 291 [doi]

Compiler Support for Reducing Leakage Energy ConsumptionWei Zhang 0002, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Vivek De. date 2003: 11146-11147 [doi]

Compiler-Directed Management of Instruction AccessesGuangyu Chen, Ismail Kadayif, Wei Zhang 0002, Mahmut T. Kandemir, Ibrahim Kolcu, Ugur Sezer. dsdm 2003: 459-462 [doi]

Implementation and Evaluation of an On-Demand Parameter-Passing Strategy for Reducing EnergyMahmut T. Kandemir, Ibrahim Kolcu, Wei Zhang 0002. date 2003: 11058-11063 [doi]

Data Space Oriented Scheduling in Embedded SystemsMahmut T. Kandemir, Guangyu Chen, Wei Zhang 0002, Ibrahim Kolcu. date 2003: 10416-10421 [doi]

Runtime Code Parallelization for On-Chip MultiprocessorsMahmut T. Kandemir, Wei Zhang 0002, Mustafa Karaköy. date 2003: 10510-10515 [doi]

Energy-Aware Parameter PassingMahmut T. Kandemir, Ibrahim Kolcu, Wei Zhang 0002. In Ahmed Amine Jerraya, Sungjoo Yoo, Diederik Verkest, Norbert Wehn, editors, Embedded Software for SoC. pages 499-512, Kluwer / Springer, 2003. [doi]

Data Space Oriented SchedulingMahmut T. Kandemir, Guangyu Chen, Wei Zhang 0002, Ibrahim Kolcu. In Ahmed Amine Jerraya, Sungjoo Yoo, Diederik Verkest, Norbert Wehn, editors, Embedded Software for SoC. pages 231-243, Kluwer / Springer, 2003. [doi]

Dynamic Parallelization of Array Based On-Chip Multiprocessor ApplicationsMahmut T. Kandemir, Wei Zhang 0002, Mustafa Karaköy. In Ahmed Amine Jerraya, Sungjoo Yoo, Diederik Verkest, Norbert Wehn, editors, Embedded Software for SoC. pages 305-318, Kluwer / Springer, 2003. [doi]

Masking the Energy Behavior of DES EncryptionHendra Saputra, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Richard R. Brooks, Soontae Kim, Wei Zhang 0002. date 2003: 10084-10089 [doi]

2002

Compiler-directed instruction cache leakage optimizationWei Zhang 0002, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. euromicro 2002: 208-218 [doi]

Compiler-directed cache polymorphismJie S. Hu, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Hendra Saputra, Wei Zhang 0002. lctrts 2002: 165-174 [doi]

2001

Exploiting VLIW schedule slacks for dynamic and leakage energy reductionWei Zhang 0002, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, David Duarte, Yuh-Fang Tsai. euromicro 2001: 102-113 [doi]

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