Abstract is missing.
- Moving from embedded systems to embedded computingJoseph A. Fisher. 1 [doi]
- Vectorizing for a SIMdD DSP architectureDorit Naishlos, Marina Biberstein, Shay Ben-David, Ayal Zaks. 2-11 [doi]
- Simple offset assignment in presence of subword dataBengu Li, Rajiv Gupta. 12-23 [doi]
- Efficient spill code for SDRAMV. Krishna Nandivada, Jens Palsberg. 24-31 [doi]
- Cluster assignment of global values for clustered VLIW processorsAndrei Terechko, Erwan Le Thenaff, Henk Corporaal. 32-40 [doi]
- Extending STI for demanding hard-real-time systemsBenjamin J. Welch, Shobhit O. Kanaujia, Adarsh Seetharam, Deepaksrivats Thirumalai, Alexander G. Dean. 41-50 [doi]
- Clustered calculation of worst-case execution timesAndreas Ermedahl, Friedhelm Stappert, Jakob Engblom. 51-62 [doi]
- Task-level timing models for guaranteed performance in multiprocessor networks-on-chipPeter Poplavko, Twan Basten, Marco Bekooij, Jef L. van Meerbergen, Bart Mesman. 63-72 [doi]
- System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architecturesJuanjo Noguera, Rosa M. Badia. 73-83 [doi]
- Reducing code size with echo instructionsJeremy Lau, Stefan Schoenmackers, Timothy Sherwood, Brad Calder. 84-94 [doi]
- Compiler optimization and ordering effects on VLIW code compressionMontserrat Ros, Peter Sutton. 95-103 [doi]
- Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensionsPartha Biswas, Nikil D. Dutt. 104-112 [doi]
- Energy aware algorithm design via probabilistic computing: from algorithms and models to Moore s law and novel (semiconductor) devicesKrishna V. Palem. 113-116 [doi]
- Frequent loop detection using efficient non-intrusive on-chip hardwareAnn Gordon-Ross, Frank Vahid. 117-124 [doi]
- Increasing the number of effective registers in a low-power processor using a windowed register fileRajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown. 125-136 [doi]
- Automatic generation of application specific processorsDavid Goodwin, Darin Petkov. 137-147 [doi]
- A scalable wide-issue clustered VLIW with a reconfigurable interconnectOsvaldo Colavin, Davide Rizzo. 148-158 [doi]
- A new look at exploiting data parallelism in embedded systemsHillery C. Hunter, Jaime H. Moreno. 159-169 [doi]
- Fault-tolerant platforms for automotive safety-critical applicationsMassimo Baleani, Alberto Ferrari, Leonardo Mangeruca, Alberto L. Sangiovanni-Vincentelli, Maurizio Peri, Saverio Pezzini. 170-177 [doi]
- Programming challenges in network processor deploymentChidamber Kulkarni, Matthias Gries, Christian Sauer, Kurt Keutzer. 178-187 [doi]
- Encryption overhead in embedded systems and sensor network nodes: modeling and analysisRamnath Venugopalan, Prasanth Ganesan, Pushkin Peddabachagari, Alexander G. Dean, Frank Mueller, Mihail L. Sichitiu. 188-197 [doi]
- AES and the cryptonite crypto processorDino Oliva, Rainer Buchty, Nevin Heintze. 198-209 [doi]
- A low-power accelerator for the SPHINX 3 speech recognition systemBinu K. Mathew, Al Davis, Zhen Fang. 210-219 [doi]
- Architectural optimizations for low-power, real-time speech recognitionRajeev Krishna, Scott A. Mahlke, Todd M. Austin. 220-231 [doi]
- Graphical user interface energy characterization for handheld computersLin Zhong, Niraj K. Jha. 232-242 [doi]
- A hierarchical approach for energy efficient application design using heterogeneous embedded systemsSumit Mohanty, Viktor K. Prasanna. 243-254 [doi]
- A control-theoretic approach to dynamic voltage schedulingAnkush Varma, Brinda Ganesh, Mainak Sen, Suchismita Roy Choudhury, Lakshmi Srinivasan, Bruce L. Jacob. 255-266 [doi]
- Power efficient encoding techniques for off-chip data busesDinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar, Laxmi N. Bhuyan. 267-275 [doi]
- Compiler-decided dynamic memory allocation for scratch-pad based embedded systemsSumesh Udayakumaran, Rajeev Barua. 276-286 [doi]
- Exploiting bank locality in multi-bank memoriesGuilin Chen, Mahmut T. Kandemir, Hendra Saputra, Mary Jane Irwin. 287-297 [doi]
- Lattice-based memory allocationAlain Darte, Robert Schreiber, Gilles Villard. 298-308 [doi]
- Performance, energy, and reliability tradeoffs in replicating hot cache linesWei Zhang 0002, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin. 309-317 [doi]
- Polynomial-time algorithm for on-chip scratchpad memory partitioningFederico Angiolini, Luca Benini, Alberto Caprara. 318-326 [doi]