Table of Contents

• Welcome to ISQED 2013Mark M. Budnik, Rasit Onur Topaloglu, Pallab Chatterjee, Keith A. Bowman, Kamesh V. Gadepally, Paul Wesling, Syed M. Alam, Rajiv V. Joshi. [doi]
• 2 3D integration: A scheme for optimizing efficiency/cost of Chip MultiprocessorsShivam Priyadarshi, Niket K. Choudhary, Brandon H. Dwiel, Ankita Upreti, Eric Rotenberg, William Rhett Davis, Paul D. Franzon. 1-7 [doi]
• Effective thermal control techniques for liquid-cooled 3D multi-core processorsYue Hu, Shaoming Chen, Lu Peng, Edward Song, Jin-Woo Choi. 8-15 [doi]
• Reliability-constrained die stacking order in 3DICs under manufacturing variabilityTuck Boon Chan, Andrew B. Kahng, Jiajia Li. 16-23 [doi]
• Analytical modeling and numerical simulations of temperature field in TSV-based 3D ICsYuriy Shiyanovskii, Christos A. Papachristou, Cheng-Wen Wu. 24-29 [doi]
• New electrical design verification approach for 2.5D/3D package signal and power integrityNozad Karim. 30 [doi]
• An arbitrary stressed NBTI compact model for analog/mixed-signal reliability simulationsJinbo Wan, Hans G. Kerkhoff. 31-37 [doi]
• Impacts of NBTI and PBTI effects on ternary CAMYen-Han Lee, Ing-Chao Lin, Sheng-Wei Wang. 38-45 [doi]
• On predicting NBTI-induced circuit aging by isolating leakage changeYinhe Han, Song Jin, Jibing Qiu, Qiang Xu, Xiaowei Li 0001. 46-52 [doi]
• Aging-aware timing analysis considering combined effects of NBTI and PBTISaman Kiamehr, Farshad Firouzi, Mehdi Baradaran Tahoori. 53-59 [doi]
• Flexible data allocation for scratch-pad memories to reduce NBTI effectsDimitra Papagiannopoulou, Patipan Prasertsom, R. Iris Bahar. 60-67 [doi]
• Runtime 3-D stacked cache management for chip-multiprocessorsJongpil Jung, Kyungsu Kang, Giovanni De Micheli, Chong-Min Kyung. 68-72 [doi]
• A co-synthesis methodology for power delivery and data interconnection networks in 3D ICsNishit Ashok Kapadia, Sudeep Pasricha. 73-79 [doi]
• Temperature aware thread migration in 3D architecture with stacked DRAMDali Zhao, Houman Homayoun, Alexander V. Veidenbaum. 80-87 [doi]
• A system-level solution for managing spatial temperature gradients in thinned 3D ICsArunachalam Annamalai, Raghavan Kumar, Arunkumar Vijayakumar, Sandip Kundu. 88-95 [doi]
• Vertically-addressed test structures (VATS) for 3D IC variability and stress measurementsConor O'Sullivan, Peter M. Levine, Siddharth Garg. 96-103 [doi]
• Energy-aware coarse-grained reconfigurable architectures using dynamically reconfigurable isolation cellsSyed M. A. H. Jafri, Ozan Bag, Ahmed Hemani, Nasim Farahini, Kolin Paul, Juha Plosila, Hannu Tenhunen. 104-111 [doi]
• Hybrid CMOS-TFET based register files for energy-efficient GPGPUsZhi Li 0016, Jingweijia Tan, Xin Fu. 112-119 [doi]
• Compiler-assisted leakage energy optimization of media applications on stream architecturesShan Cao, Zhaolin Li, Zhixiang Chen, Guoyue Jiang, Shaojun Wei. 120-127 [doi]
• On a rewriting strategy for dynamically managing power constraints and power dissipation in SoCsVinod Viswanath, Rajeev Muralidhar, Harinarayanan Seshadri, Jacob A. Abraham. 128-134 [doi]
• Sustainable dual-level DVFS-enabled NoC with on-chip wireless linksJacob Murray, Rajath Hegde, Teng Lu, Partha Pratim Pande, Behrooz Shirazi. 135-142 [doi]
• On the selection of adder unit in energy efficient vector processingIvan Ratkovic, Oscar Palomar, Milan Stanic, Osman S. Unsal, Adrián Cristal, Mateo Valero. 143-150 [doi]
• Low-energy digital filter design based on controlled timing error acceptanceKu He, Andreas Gerstlauer, Michael Orshansky. 151-157 [doi]
• A novel and efficient method for power pad placement optimizationTing Yu, Martin D. F. Wong. 158-163 [doi]
• Min-cut based leakage power aware scheduling in high-level synthesisNan Wang, Song Chen, Takeshi Yoshimura. 164-169 [doi]
• Hierarchical dynamic power management using model-free reinforcement learningYanzhi Wang, Maryam Triki, Xue Lin, Ahmed C. Ammari, Massoud Pedram. 170-177 [doi]
• Accurate architecture-level thermal analysis methods for MPSoC with consideration for leakage power dependence on temperatureJiaqi Yan, Zuying Luo, Liang Tang. 178-183 [doi]
• Application-driven power efficient ALU design methodology for modern microprocessorsNa Gong, Jinhui Wang, Ramalingam Sridhar. 184-188 [doi]
• Low power and compact mixed-mode signal processing hardware using spin-neuronsMrigank Sharad, Deliang Fan, Kaushik Roy. 189-195 [doi]
• System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETsChenyun Pan, Ahmet Ceyhan, Azad Naeemi. 196-202 [doi]
• Impact of conventional and emerging interconnects on the circuit performance of various post-CMOS devicesAhmet Ceyhan, Azad Naeemi. 203-209 [doi]
• Reducing IR drop in 3D integration to less than 1/4 using Buck Converter on Top die (BCT) schemeYasuhiro Shinozuka, Hiroshi Fuketa, Koichi Ishida, Futoshi Furuta, Kenichi Osada, Kenichi Takeda, Makoto Takamiya, Takayasu Sakurai. 210-215 [doi]
• Energy-efficient Spin-Transfer Torque RAM cache exploiting additional all-zero-data flagsJinwook Jung, Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi. 216-222 [doi]
• Design of ultra high density and low power computational blocks using nano-magnetsMrigank Sharad, Karthik Yogendra, Kon-Woo Kwon, Kaushik Roy. 223-230 [doi]
• LMgr: A low-M emory global router with dynamic topology update and bending-aware optimum path searchJingwei Lu, Chiu-Wing Sham. 231-238 [doi]
• Vision-inspired global routing for enhanced performance and reliabilityJun Yong Shin, Nikil Dutt, Fadi J. Kurdahi. 239-244 [doi]
• Crosstalk timing windows overlap in statistical static timing analysisHanif Fatemi, Peivand Tehrani. 245-251 [doi]
• Multi-objective optimization algorithm for efficient pin-constrained droplet routing technique in digital microfluidic biochipSoumyajit Chatterjee, Hafizur Rahaman, Tuhina Samanta. 252-256 [doi]
• Advances in wire routingMartin D. F. Wong. 257 [doi]
• Effectiveness of hybrid recovery techniques on parametric failuresShrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio. 258-264 [doi]
• Fast reliability exploration for embedded processors via high-level fault injectionZheng Wang, Chao Chen, Anupam Chattopadhyay. 265-272 [doi]
• Analysis and reliability test to improve the data retention performance of EPROM circuitsJiyuan Luan, Michael DiVita. 273-277 [doi]
• Enabling sizing for enhancing the static noise marginsValeriu Beiu, Azam Beg, Walid Ibrahim, Fekri Kharbash, Massimo Alioto. 278-285 [doi]
• SRAM bit-line electromigration mechanism and its prevention schemeZhong Guan, Malgorzata Marek-Sadowska, Sani R. Nassif. 286-293 [doi]
• Cost-driven 3D design optimization with metal layer reduction techniqueQiaosha Zou, Jing Xie, Yuan Xie. 294-299 [doi]
• TSV-aware topology generation for 3D Clock Tree SynthesisWulong Liu, Haixiao Du, Yu Wang 0002, Yuchun Ma, Yuan Xie, Jinguo Quan, Huazhong Yang. 300-307 [doi]
• Electrical and thermal analysis for design exchange formats in three dimensional integrated circuitsRishik Bazaz, Jianyong Xie, Madhavan Swaminathan. 308-315 [doi]
• Reliability consideration with rectangle- and double-signal through silicon vias insertion in 3D thermal-aware floorplanningChih-han Hsu, Shanq-Jang Ruan, Ying-Jung Chen, Tsang-Chi Kan. 316-321 [doi]
• Configurable redundant via-aware standard cell design considering multi-via mechanismTsang-Chi Kan, Hung-Ming Hong, Ying-Jung Chen, Shanq-Jang Ruan. 322-326 [doi]
• A novel flow for reducing clock skew considering NBTI effect and process variationsJifeng Chen, Mohammad Tehranipoor. 327-334 [doi]
• Suspicious timing error prediction with in-cycle clock gatingYouhua Shi, Hiroaki Igarashi, Nozomu Togawa, Masao Yanagisawa. 335-340 [doi]
• Performance entitlement by exploiting transistor's BTI recoverySenthil Arasu, Mehrdad Nourani, Vijay Reddy, John M. Carulli. 341-346 [doi]
• Device design and analysis of logic circuits and SRAMs for Germanium FinFETs on SOI and bulk substratesVita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang. 347-352 [doi]
• A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write abilityShairfe Muhammad Salahuddin, Hailong Jiao, Volkan Kursun. 353-358 [doi]
• Canonical ordering of instances to immunize the FPGA place and route flow from ECO-induced varianceAvijit Dutta, Neil Tuttle, Krishnan Anandh. 359-363 [doi]
• A low power detection routing method for bufferless NoCChung-Kai Hsu, Kun-Lin Tsai, Jing-Fu Jheng, Shanq-Jang Ruan, Chung-An Shen. 364-367 [doi]
• A 64-core platform for biomedical signal processingJordan Bisasky, Houman Homayoun, Farhang Yazdani, Tinoosh Mohsenin. 368-372 [doi]
• Improving timing error tolerance without impact on chip area and power consumptionKen Yano, Takanori Hayashida, Toshinori Sato. 373-378 [doi]
• System-level modelling of dynamic reconfigurable designs using functional programming abstractionsBahram N. Uchevler, Kjetil Svarstad, Jan Kuper, Christiaan Baaij. 379-385 [doi]
• Design of a 6 Gbps continuous-time adaptive equalizer using a voltage rectifier instead of a power detectorKrishna Srinivasan, Jonathan Rosenfeld. 386-390 [doi]
• A predictable compact model for non-monotonous Vth-Pelgrom plot of long channel halo-implanted transistorsShigetaka Kumashiro. 391-397 [doi]
• Manufacturable nanometer designs using standard cells with regular layoutKasyab P. Subramaniyan, Per Larsson-Edefors. 398-405 [doi]
• Fast analog design optimization using regression-based modeling and genetic algorithm: A nano-CMOS VCO case studyDhruva Ghai, Saraju P. Mohanty, Garima Thakral. 406-411 [doi]
• Low power sensor for temperature compensation in molecular biosensingDaniela De Venuto. 412-415 [doi]
• A power efficient and digitally assisted CMOS complementary telescopic amplifier with wide input common mode rangeRishi Todani, Ashis Kumar Mal. 416-421 [doi]
• Peak power reduction of a sensor network processor fabricated with Deeply Depleted Channel transistors in 65nm technologyKentaro Kawakami, Takeshi Shiro, Hironobu Yamasaki, Katsuhiro Yoda, Hiroaki Fujimoto, Kenichi Kawasaki, Yasuhiro Watanabe. 422-429 [doi]
• Evaluation of tunnel FET-based flip-flop designs for low power, high performance applicationsMatthew Cotter, Huichu Liu, Suman Datta, Vijaykrishnan Narayanan. 430-437 [doi]
• A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitryKoji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, Yuichiro Ishii, Tetsuya Matsumura, Yoshio Matsuda. 438-441 [doi]
• CPDI: Cross-power-domain interface circuit design in monolithic 3D technologyJing Xie, Yang Du, Yuan Xie. 442-447 [doi]
• Impact of process parameter and supply voltage fluctuations on multi-threshold-voltage seven-transistor static memory cellsHong Zhu, Volkan Kursun. 448-453 [doi]
• Input-aware statistical timing analysis-based delay test pattern generationBao Liu, Lu Wang. 454-459 [doi]
• Effect-cause intra-cell diagnosis at transistor levelZhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Etienne Auvray. 460-467 [doi]
• Framework for analog test coverageDebesh Bhatta, Ishita Mukhopadhyay, Suriyaprakash Natarajan, Prashant Goteti, Bin Xue. 468-475 [doi]
• Fast FPGA-based fault injection tool for embedded processorsMohammad Shokrolah-Shirazi, Brendan Morris, Henry Selvaraj. 476-480 [doi]
• Diagnosis of small delay defects arising due to manufacturing imperfections using path delay measurementsAhish Mysore Somashekar, Spyros Tragoudas. 481-486 [doi]
• Tabu search based cells placement in nanofabric architectures with restricted connectivitySadiq M. Sait, Abdalrahman M. Arafeh. 487-493 [doi]
• Relocatable and resizable SRAM synthesis for via configurable structured ASICHsin-Hung Liu, Rung-Bin Lin, I.-Lun Tseng. 494-501 [doi]
• Cost-efficient scheduling in high-level synthesis for Soft-Error Vulnerability MitigationYuko Hara-Azumi, Hiroyuki Tomiyama. 502-507 [doi]
• Analysis of very large resistive networks using low distortion embeddingSandeep Koranne. 508-515 [doi]
• Efficient translation validation of high-level synthesisTun Li, Yang Guo, Wanwei Liu, Chiyuan Ma. 516-523 [doi]
• Performance and cache access time of SRAM-eDRAM hybrid caches considering wire delayYoung-Ho Gong, Hyung Beom Jang, Sung Woo Chung. 524-530 [doi]
• Increasing the security level of analog IPs by using a dedicated vulnerability analysis methodologyNoemie Beringuier-Boher, David Hély, Vincent Beroulle, Joel Damiens, Philippe Candelier. 531-537 [doi]
• High-speed DFG-level SEU vulnerability analysis for applying selective TMR to resource-constrained CGRATakashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato. 538-545 [doi]
• Geostatistics inspired fast layout optimization of nanoscale CMOS phase locked loopOghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos. 546-551 [doi]
• Performance validation through implicit removal of infeasible paths of the behavioral descriptionDheepakkumaran Jayaraman, Spyros Tragoudas. 552-557 [doi]
• Early system level modeling of real-time applications on embedded platformsRichard Lee, Karim Abdel-Khalek, Samar Abdi, Frederic Risacher. 558-565 [doi]
• SUALD: Spacing uniformity-aware layout decomposition in triple patterning lithographyZihao Chen, Hailong Yao, Yici Cai. 566-571 [doi]
• Stochastic behavioral modeling of analog/mixed-signal circuits by maximizing entropyRahul Krishnan, Wei Wu, Fang Gong, Lei He. 572-579 [doi]
• Analysis, modeling and silicon correlation of low-voltage flop data retention in 28nm process technologyAnimesh Datta, Mohamed H. Abu-Rahma, Sachin Dileep Dasnurkar, Hadi Rasouli, Sean Tamjidi, Ming Cai, Samit Sengupta, P. R. Chidambaram, Raghavan Thirumala, Nikhil Kulkarni, Prasanna Seeram, Prasad Bhadri, Prayag Patel, Sei Seung Yoon, Esin Terzioglu. 580-584 [doi]
• A comparator energy model considering shallow trench isolation stress by geometric programmingGong Chen, Yu Zhang, Bo Yang 0004, Qing Dong, Shigetoshi Nakatake. 585-590 [doi]
• Wire delay variability in nanoscale technology and its impact on physical designSani R. Nassif, Gi-Joon Nam, Shayak Banerjee. 591-596 [doi]
• Multi-trap RTN parameter extraction based on Bayesian inferenceHiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato. 597-602 [doi]
• VERVE: A framework for variation-aware energy efficient synthesis of NoC-based MPSoCs with voltage islandsNishit Ashok Kapadia, Sudeep Pasricha. 603-610 [doi]
• A virtualization approach for MIPS-based MPSoCsAlexandra Aguiar, Carlos Moratelli, Marcos Sartori, Fabiano Hessel. 611-618 [doi]
• Thermal-aware semi-dynamic power management for multicore systems with energy harvestingYi Xiang, Sudeep Pasricha. 619-626 [doi]
• On the interactions between real-time scheduling and inter-thread cached interferences for multicore processorsYiqiang Ding, Wei Zhang 0002. 627-634 [doi]
• Resource allocation and consolidation in a multi-core server cluster using a Markov decision process modelYanzhi Wang, Shuang Chen, Hadi Goudarzi, Massoud Pedram. 635-642 [doi]
• Reliability-aware and energy-efficient synthesis of NoC based MPSoCsYong Zou, Sudeep Pasricha. 643-650 [doi]
• CMOS inverter delay model based on DC transfer curve for slow inputFelipe S. Marranghello, André Inácio Reis, Renato P. Ribas. 651-657 [doi]
• RF passive device modeling and characterization in 65nm CMOS technologyErrikos Lourandakis, Stefanos Stefanou, Konstantinos Nikellis, Sotiris Bantas. 658-664 [doi]
• An efficient method for ECSM characterization of CMOS inverter in nanometer range technologiesBaljit Kaur, Sandeep Miryala, S. K. Manhas, Bulusu Anand. 665-669 [doi]
• Power Integrity analysis and discrete optimization of decoupling capacitors on high speed power planes by particle swarm optimizationJai Narayan Tripathi, Raj Kumar Nagpal, Nitin Kumar Chhabra, Rakesh Malik, Jayanta Mukherjee, Prakash R. Apte. 670-675 [doi]
• A method to determine the sensitization probability of a non-robustly testable pathDheepakkumaran Jayaraman, Spyros Tragoudas. 676-681 [doi]
• A power-efficient on-chip linear regulator assisted by switched capacitors for fast transient regulationSuming Lai, Peng Li. 682-688 [doi]
• A versatile rail to rail current mode instrumentation amplifier with an embedded band-pass filter for bio-potential signal conditioningAmaravati Anvesha, Maryam Shojaei Baghini. 689-695 [doi]
• 2 ring oscillator based temperature sensor for on-chip thermal managementNicolo Testi, Yang Xu. 696-702 [doi]
• Analysis and comparison of XOR cell structures for low voltage circuit designShinichi Nishizawa, Tohru Ishihara, Hidetoshi Onodera. 703-708 [doi]
• A CMOS high dimming ratio power-LED driver with a preloading inductor current methodKwang S. Yoon, Keon Lee. 709-713 [doi]
• Minimizing simultaneous switching noise at reduced power with constant-voltage power transmission lines for high-speed signalingSatyanarayana Telikepalli, Madhavan Swaminathan, David C. Keezer. 714-718 [doi]
• Reliable Express-Virtual-Channel-based network-on-chip under the impact of technology scalingXin Fu, Tao Li, José A. B. Fortes. 719-726 [doi]
• Clustering techniques and statistical fault injection for selective mitigation of SEUs in flip-flopsAdrian Evans, Michael Nicolaidis, Shi-Jie Wen, Thiago Asis. 727-732 [doi]
• Easy-to-build Arbiter Physical Unclonable Function with enhanced challenge/response setDinesh Ganta, Leyla Nazhandali. 733-738 [doi]