Abstract is missing.
- Cherry: checkpointed early resource recycling in out-of-order microprocessorsJosé F. Martínez, Jose Renau, Michael C. Huang, Milos Prvulovic, Josep Torrellas. 3-14 [doi]
- Characterizing and predicting value degree of useJ. Adam Butts, Gurindar S. Sohi. 15-26 [doi]
- Hierarchical Scheduling WindowsEdward Brekelbaum, Jeff Rupley, Chris Wilkerson, Bryan Black. 27-36 [doi]
- Three extensions to register integrationVlad Petric, Anne Bracy, Amir Roth. 37-47 [doi]
- Instruction fetch deferral using static slackGregory A. Muthler, David Crowe, Sanjay J. Patel, Steven Lumetta. 51-61 [doi]
- Pointer cache assisted prefetchingJamison D. Collins, Suleyman Sair, Brad Calder, Dean M. Tullsen. 62-73 [doi]
- Microarchitectural support for precomputation microthreadsRobert S. Chappell, Francis Tseng, Adi Yoaz, Yale N. Patt. 74-84 [doi]
- Master/slave speculative parallelizationCraig B. Zilles, Gurindar S. Sohi. 85-96 [doi]
- Reduced code size modulo scheduling in the absence of hardware supportJosep Llosa, Stefan M. Freudenberger. 99-110 [doi]
- Convergent schedulingWalter Lee, Diego Puppin, Shane Swenson, Saman P. Amarasinghe. 111-122 [doi]
- Effective instruction scheduling techniques for an interleaved cache clustered VLIW processorEnric Gibert, F. Jesús Sánchez, Antonio González. 123-133 [doi]
- Compiler managed micro-cache bypassing for high performance EPIC processorsYoufeng Wu, Ryan Rakvic, Li-Ling Chen, Chyi-Chang Miao, George Chrysos, Jesse Fang. 134-145 [doi]
- Three-dimensional memory vectorization for high bandwidth media memory systemsJesús Corbal, Roger Espasa, Mateo Valero. 149-160 [doi]
- Dynamic addressing memory arrays with physical localitySteven Hsu, Shih-Lien Lu, Shih-Chang Lai, Ram Krishnamurthy, Konrad Lai. 161-170 [doi]
- Reducing register ports for higher speed and lower energyIl Park, Michael D. Powell, T. N. Vijaykumar. 171-182 [doi]
- Generating physical addresses directly for saving instruction TLB energyIsmail Kadayif, Anand Sivasubramaniam, Mahmut T. Kandemir, Gokul B. Kandiraju, Guangyu Chen. 185-196 [doi]
- Energy efficient frequent value data cache designJun Yang, Rajiv Gupta. 197-207 [doi]
- Compiler-directed instruction cache leakage optimizationWei Zhang 0002, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. 208-218 [doi]
- Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank predictionNam Sung Kim, Krisztián Flautner, David Blaauw, Trevor N. Mudge. 219-230 [doi]
- Vacuum packing: extracting hardware-detected program phases for post-link optimizationRonald D. Barnes, Erik M. Nystrom, Matthew C. Merten, Wen-mei W. Hwu. 233-244 [doi]
- A faster optimal register allocatorChangqing Fu, Kent D. Wilken. 245-256 [doi]
- DELI: a new run-time control pointGiuseppe Desoli, Nikolay Mateev, Evelyn Duesterwald, Paolo Faraboschi, Joseph A. Fisher. 257-268 [doi]
- Microarchitectural exploration with LibertyManish Vachharajani, Neil Vachharajani, David A. Penry, Jason A. Blome, David I. August. 271-282 [doi]
- Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarksChristoforos E. Kozyrakis, David A. Patterson. 283-293 [doi]
- Orion: a power-performance simulator for interconnection networksHangsheng Wang, Xinping Zhu, Li-Shiuan Peh, Sharad Malik. 294-305 [doi]
- Using modern graphics architectures for general-purpose computing: a framework and analysisChris J. Thompson, Sahngyun Hahn, Mark Oskin. 306-317 [doi]
- Managing static leakage energy in microprocessor functional unitsSteve Dropsho, Volkan Kursun, David H. Albonesi, Sandhya Dwarkadas, Eby G. Friedman. 321-332 [doi]
- Optimizing pipelines for power and performanceViji Srinivasan, David Brooks, Michael Gschwind, Pradip Bose, Victor V. Zyuban, Philip N. Strenski, Philip G. Emma. 333-344 [doi]
- Power protocol: reducing power dissipation on off-chip data busesK. Basu, Alok N. Choudhary, Jayaprakash Pisharath, Mahmut T. Kandemir. 345-355 [doi]
- Dynamic frequency and voltage control for a multiple clock domain microarchitectureGreg Semeraro, David H. Albonesi, Steve Dropsho, Grigorios Magklis, Sandhya Dwarkadas, Michael L. Scott. 356-367 [doi]
- Fetching instruction streamsAlex Ramírez, Oliverio J. Santana, Josep-Lluis Larriba-Pey, Mateo Valero. 371-382 [doi]
- Register write specialization register read specialization: a path to complexity-effective wide-issue superscalar processorsAndré Seznec, Eric Toullec, Olivier Rochecouste. 383-394 [doi]
- Exploiting data-width locality to increase superscalar execution bandwidthGabriel H. Loh. 395-405 [doi]
- Microarchitectural denial of service: insuring microarchitectural fairnessDirk Grunwald, Soraya Ghiasi. 409-418 [doi]
- Compiling for instruction cache performance on a multithreaded architectureRakesh Kumar, Dean M. Tullsen. 419-429 [doi]
- A quantitative framework for automated pre-execution thread selectionAmir Roth, Gurindar S. Sohi. 430-441 [doi]