Abstract is missing.
- High level formal verification of next-generation microprocessorsThomas Schubert. 1-6 [doi]
- Verification strategy for integration 3G baseband SoCYves Mathys, André Chátelain. 7-10 [doi]
- Improvements in functional simulation addressing challenges in large, distributed industry projectsKlaus-Dieter Schubert. 11-14 [doi]
- Reshaping EDA for powerJan M. Rabaey, Dennis Sylvester, David Blaauw, Kerry Bernstein, Jerry Frenkil, Mark Horowitz, Wolfgang Nebel, Takayasu Sakurai, Andrew Yang. 15 [doi]
- A cost-driven lithographic correction methodology based on off-the-shelf sizing toolsPuneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang. 16-21 [doi]
- Performance-impact limited area fill synthesisYu Chen, Puneet Gupta, Andrew B. Kahng. 22-27 [doi]
- Improved global routing through congestion estimationRaia Hadsell, Patrick H. Madden. 28-31 [doi]
- Microarchitecture evaluation with physical planningJason Cong, Ashok Jagannathan, Glenn Reinman, Michail Romesis. 32-35 [doi]
- Energy-aware design techniques for differential power analysis protectionLuca Benini, Alberto Macii, Enrico Macii, Elvira Omerbegovic, Fabrizio Pro, Massimo Poncino. 36-41 [doi]
- A timing-accurate modeling and simulation environment for networked embedded systemsFranco Fummi, Giovanni Perbellini, Paolo Gallo, Massimo Poncino, Stefano Martini, Fabio Ricciato. 42-47 [doi]
- Application of design patterns for hardware designRobertas Damasevicius, Giedrius Majauskas, Vytautas Stuikys. 48-53 [doi]
- A fully-programmable memory management system optimizing queue handling at multi-gigabit ratesGeorge Kornaros, Ioannis Papaefstathiou, Aristides Nikologiannis, Nicholaos Zervos. 54-59 [doi]
- Design flow for HW / SW acceleration transparency in the thumbpod secure embedded systemDavid Hwang, Bo-Cheng Lai, Patrick Schaumont, Kazuo Sakiyama, Yi Fan, Shenglin Yang, Alireza Hodjat, Ingrid Verbauwhede. 60-65 [doi]
- Design techniques for sensor appliances: foundations and light compass case studyJennifer L. Wong, Seapahn Megerian, Miodrag Potkonjak. 66-71 [doi]
- Seamless multi-radio integration challengesUri Barkai. 72 [doi]
- RF front end application and technology trendsPieter W. Hooijmans. 73-78 [doi]
- 4G terminals: how are we going to design them?Jan Craninckx, Stéphane Donnay. 79-84 [doi]
- New techniques for non-linear behavioral modeling of microwave/RF ICs from simulation and nonlinear microwave measurementsDavid E. Root, John Wood, Nick Tufillaro. 85-90 [doi]
- COT - customer owned troubleRobert Dahlberg, Shishpal Rawat, Jen Bernier, Gina Gloski, Aurangzeb Khan, Kaushik Patel, Paul Ruddy, Naveed A. Sherwani, Ronnie Vasishta. 91-92 [doi]
- Random walks in a supply networkHaifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar. 93-98 [doi]
- A static pattern-independent technique for power grid voltage integrity verificationDionysios Kouroussis, Farid N. Najm. 99-104 [doi]
- Power network analysis using an adaptive algebraic multigrid approachZhengyong Zhu, Bo Yao, Chung-Kuan Cheng. 105-108 [doi]
- Power grid reduction based on algebraic multigrid principlesHaihua Su, Emrah Acar, Sani R. Nassif. 109-112 [doi]
- On-chip power supply network optimization using multigrid-based techniqueKai Wang, Malgorzata Marek-Sadowska. 113-118 [doi]
- Scalable modeling and optimization of mode transitions based on decoupled power management architectureDexin Li, Qiang Xie, Pai H. Chou. 119-124 [doi]
- Optimal voltage allocation techniques for dynamically variable voltage processorsWoo-Cheol Kwon, Taewhan Kim. 125-130 [doi]
- Energy reduction techniques for multimedia applications with tolerance to deadline missesShaoxiong Hua, Gang Qu, Shuvra S. Bhattacharyya. 131-136 [doi]
- Xtream-Fit: an energy-delay efficient data memory subsystem for embedded media processingAnand Ramachandran, Margarida F. Jacome. 137-142 [doi]
- A new enhanced constructive decomposition and mapping algorithmAlan Mishchenko, Xinning Wang, Timothy Kam. 143-148 [doi]
- Large-scale SOP minimization using decomposition and functional propertiesAlan Mishchenko, Tsutomu Sasao. 149-154 [doi]
- Generalized cofactoring for logic function evaluationYunjian Jiang, Slobodan Matic, Robert K. Brayton. 155-158 [doi]
- Making cyclic circuits acyclicStephen A. Edwards. 159-162 [doi]
- The synthesis of cyclic combinational circuitsMarc D. Riedel, Jehoshua Bruck. 163-168 [doi]
- Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modelingSaibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy. 169-174 [doi]
- Analysis and minimization techniques for total leakage considering gate oxide leakageDongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester. 175-180 [doi]
- Distributed sleep transistor network for power reductionChangbo Long, Lei He. 181-186 [doi]
- Implications of technology scaling on leakage reduction techniquesYuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin. 187-190 [doi]
- Static leakage reduction through simultaneous threshold voltage and state assignmentDongwoo Lee, David Blaauw. 191-194 [doi]
- Emerging markets: design goes globalChi-Foon Chan, Deirdre Hanford, Jian Yue Pan, Narendra V. Shenoy, Mahesh Mehendale, A. Vasudevan, Shaojun Wei. 195 [doi]
- Timing optimization of FPGA placements by logic replicationGiancarlo Beraudo, John Lillis. 196-201 [doi]
- Delay budgeting in sequential circuit with application on FPGA placementChao-Yang Yeh, Malgorzata Marek-Sadowska. 202-207 [doi]
- Multilevel global placement with retimingJason Cong, Xin Yuan. 208-213 [doi]
- Force directed mongrel with physical net constraintsSung-Woo Hur, Tung Cao, Karthik Rajagopal, Yegna Parasuram, Amit Chowdhary, Vladimir Tiourin, Bill Halpin. 214-219 [doi]
- Realizable parasitic reduction using generalized Y-Delta transformationZhanhai Qin, Chung-Kuan Cheng. 220-225 [doi]
- Realizable RLCK circuit crunchingChirayu S. Amin, Masud H. Chowdhury, Yehea I. Ismail. 226-231 [doi]
- Efficient model order reduction including skin effectShizhong Mei, Chirayu S. Amin, Yehea I. Ismail. 232-237 [doi]
- Model order reduction of nonuniform transmission lines using integrated congruence transformEmad Gad, Michel S. Nakhla. 238-243 [doi]
- Partial task assignment of task graphs under heterogeneous resource constraintsRadoslaw Szymanek, Krzysztof Kuchcinski. 244-249 [doi]
- Dynamic hardware/software partitioning: a first approachGreg Stitt, Roman L. Lysecky, Frank Vahid. 250-255 [doi]
- Automatic application-specific instruction-set extensions under microarchitectural constraintsKubilay Atasu, Laura Pozzi, Paolo Ienne. 256-261 [doi]
- Instruction encoding synthesis for architecture exploration using hierarchical processor modelsAchim Nohl, Volker Greive, Gunnar Braun, Andreas Hoffmann, Rainer Leupers, Oliver Schliebusch, Heinrich Meyr. 262-267 [doi]
- Quantum-dot cellular automata: computing by field polarizationGary H. Bernstein. 268-273 [doi]
- Recent advances and future prospects in single-electronicsChristoph Wasshuber. 274-275 [doi]
- Manipulation and characterization of molecular scale componentsIslamshah Amlani, Ruth Zhang, John Tresek, Larry Nagahara, Raymond K. Tsui. 276-277 [doi]
- Mixed signals on mixed-signal: the right next technologyRob A. Rutenbar, David L. Harame, Kurt Johnson, Paul Kempf, Teresa H. Y. Meng, Reza Rofougaran, James Spoto. 278-279 [doi]
- Coverage-oriented verification of baniasAlon Gluska. 280-285 [doi]
- Coverage directed test generation for functional verification using bayesian networksShai Fine, Avi Ziv. 286-291 [doi]
- Dos and don ts of CTL state coverage estimationNikhil Jayakumar, Mitra Purandare, Fabio Somenzi. 292-295 [doi]
- Constraint synthesis for environment modeling in functional verificationJun Yuan, Ken Albin, Adnan Aziz, Carl Pixley. 296-299 [doi]
- Automatic communication refinement for system level designSamar Abdi, Dongwan Shin, Daniel Gajski. 300-305 [doi]
- CoCo: a hardware/software platform for rapid prototyping of code compression technologiesHaris Lekatsas, Jörg Henkel, Srimat T. Chakradhar, Venkata Jakkula, Murugan Sankaradass. 306-311 [doi]
- A tool for describing and evaluating hierarchical real-time bus scheduling policiesTrevor Meyerowitz, Claudio Pinello, Alberto L. Sangiovanni-Vincentelli. 312-317 [doi]
- A transformation based algorithm for reversible logic synthesisD. Michael Miller, Dmitri Maslov, Gerhard W. Dueck. 318-323 [doi]
- An arbitrary twoqubit computation In 23 elementary gates or lessStephen S. Bullock, Igor L. Markov. 324-329 [doi]
- Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstractionArash Saifhashemi, Hossein Pedram. 330-333 [doi]
- On-chip logic minimizationRoman L. Lysecky, Frank Vahid. 334-337 [doi]
- Parameter variations and impact on circuits and microarchitectureShekhar Borkar, Tanay Karnik, Siva Narendra, James Tschanz, Ali Keshavarzi, Vivek De. 338-342 [doi]
- Death, taxes and failing chipsChandu Visweswariah. 343-347 [doi]
- Computation and Refinement of Statistical Bounds on Circuit DelayAseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula. 348-353 [doi]
- Fast, cheap and under control: the next implementation fabricAbbas El Gamal, Ivo Bolsens, Andy Broom, Christopher Hamlin, Philippe Magarshack, Zvi Or-Bach, Lawrence T. Pileggi. 354-355 [doi]
- Using a formal specification and a model checker to monitor and direct simulationSerdar Tasiran, Yuan Yu, Brannon Batson. 356-361 [doi]
- Advanced techniques for RTL debuggingYu-Chin Hsu, Bassam Tabbara, Yirng-An Chen, Fur-Shing Tsai. 362-367 [doi]
- Behavioral consistency of C and verilog programs using bounded model checkingEdmund M. Clarke, Daniel Kroening, Karen Yorav. 368-371 [doi]
- Re-use-centric architecture for a fully accelerated testbench environmentRenate Henftling, Andreas Zinn, Matthias Bauer, Martin Zambaldi, Wolfgang Ecker. 372-375 [doi]
- An effective capacitance based driver output model for on-chip RLC interconnectsKanak Agarwal, Dennis Sylvester, David Blaauw. 376-381 [doi]
- Delay and slew metrics using the lognormal distributionCharles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan. 382-385 [doi]
- Blade and razor: cell and interconnect delay analysis using current-based modelsJohn F. Croix, D. F. Wong. 386-389 [doi]
- Non-iterative switching window computation for delay-noiseBhavana Thudi, David Blaauw. 390-395 [doi]
- Architecture-level performance evaluation of component-based embedded systemsJeffry T. Russell, Margarida F. Jacome. 396-401 [doi]
- An IDF-based trace transformation method for communication refinementAndy D. Pimentel, Cagkan Erbas. 402-407 [doi]
- Schedulers as model-based design elements in programmable heterogeneous multiprocessorsJoAnn M. Paul, Alex Bobrek, Jeffrey E. Nelson, Joshua J. Pieper, Donald E. Thomas. 408-411 [doi]
- A complexity effective communication model for behavioral modeling of signal processing applicationsSatya Kiran, M. N. Jayram, Pradeep Rao, S. K. Nandy. 412-415 [doi]
- Leading-edge and future design challenges - is the classical EDA ready?Greg Spirakis. 416 [doi]
- How to make efficient communication, collaboration, and optimization from system to chipAkira Matsuzawa. 417-418 [doi]
- System-on-chip beyond the nanometer wallPhilippe Magarshack, Pierre G. Paulin. 419-424 [doi]
- A hybrid SAT-based decision procedure for separation logic with uninterpreted functionsSanjit A. Seshia, Shuvendu K. Lahiri, Randal E. Bryant. 425-430 [doi]
- Symbolic representation with ordered function templatesAmit Goel, Gagan Hasteer, Randal E. Bryant. 431-435 [doi]
- A signal correlation guided ATPG solver and its applications for solving difficult industrial casesFeng Lu, Li-C. Wang, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna. 436-441 [doi]
- Solving the latch mapping problem in an industrial settingKelvin Ng, Mukul R. Prasad, Rajarshi Mukherjee, Jawahar Jain. 442-447 [doi]
- Static analysis of transaction-level modelsGiovanni Agosta, Francesco Bruschi, Donatella Sciuto. 448-453 [doi]
- Enabling scheduling analysis of heterogeneous systems with multi-rate data dependencies and rate intervalsMarek Jersak, Rolf Ernst. 454-459 [doi]
- Automatic trace analysis for logic of constraintsXi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe. 460-465 [doi]
- Accurate timing analysis by modeling caches, speculation and their interactionXianfeng Li, Tulika Mitra, Abhik Roychoudhury. 466-471 [doi]
- NORM: compact model order reduction of weakly nonlinear systemsPeng Li, Lawrence T. Pileggi. 472-477 [doi]
- Analog and RF circuit macromodels for system-level analysisXin Li, Peng Li, Yang Xu, Lawrence T. Pileggi. 478-483 [doi]
- Piecewise polynomial nonlinear model reductionNing Dong, Jaijeet S. Roychowdhury. 484-489 [doi]
- A TBR-based trajectory piecewise-linear algorithm for generating accurate low-order models for nonlinear analog circuits and MEMSDmitry Vasilyev, Michal Rewienski, Jacob White. 490-495 [doi]
- Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modelingClaire Fang Fang, Rob A. Rutenbar, Markus Püschel, Tsuhan Chen. 496-501 [doi]
- Automating the design of an asynchronous DLX microprocessorManish Amde, Ivan Blunno, Christos P. Sotiriou. 502-507 [doi]
- High-level synthesis of asynchronous systems by data-driven decompositionCatherine G. Wong, Alain J. Martin. 508-513 [doi]
- Using estimates from behavioral synthesis tools in compiler-directed design space explorationByoungro So, Pedro C. Diniz, Mary W. Hall. 514-519 [doi]
- A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock referenceRobert M. Senger, Eric D. Marsman, Michael S. McCorquodale, Fadi H. Gebara, Keith L. Kraver, Matthew R. Guthaus, Richard B. Brown. 520-525 [doi]
- Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithmCharlotte Y. Lau, Michael H. Perrott. 526-531 [doi]
- Characterizing the effects of clock jitter due to substrate noise in discrete-time D/S modulatorsPayam Heydari. 532-537 [doi]
- Computation of noise spectral density in switched capacitor circuits using the mixed-frequency-time techniqueVinita Vasudevan, M. Ramakrishna. 538-541 [doi]
- Symbolic analysis of analog circuits with hard nonlinearityAlicia Manthe, Zhao Li, C.-J. Richard Shi. 542-545 [doi]
- Nanometer design: place your betsAndrew B. Kahng, Shekhar Borkar, John M. Cohn, Antun Domic, Patrick Groeneveld, Louis Scheffer, Jean-Pierre Schoellkopf. 546-547 [doi]
- A scalable software-based self-test methodology for programmable processorsLi Chen, Srivaths Ravi, Anand Raghunathan, Sujit Dey. 548-553 [doi]
- A scan BIST generation method using a markov source and partial bit-fixingWei Li, Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz. 554-559 [doi]
- Seed encoding with LFSRs and cellular automataAhmad A. Al-Yamani, Edward J. McCluskey. 560-565 [doi]
- Efficient compression and application of deterministic patterns in a logic BIST architecturePeter Wohl, John A. Waicukauski, Sanjay Patel, Minesh B. Amin. 566-569 [doi]
- Ultimate low cost analog BISTMarcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin. 570-573 [doi]
- Gain-based technology mapping for discrete-size cell librariesBo Hu, Yosinori Watanabe, Alex Kondratyev, Malgorzata Marek-Sadowska. 574-579 [doi]
- An O(nlogn) time algorithm for optimal buffer insertionWeiping Shi, Zhuo Li. 580-585 [doi]
- Optimum positioning of interleaved repeaters In bidirectional busesMaged Ghoneima, Yehea I. Ismail. 586-591 [doi]
- Synthesizing optimal filters for crosstalk-cancellation for high-speed busesJihong Ren, Mark R. Greenstreet. 592-597 [doi]
- Fast timing-driven partitioning-based placement for island style FPGAsPongstorn Maidee, Cristinel Ababei, Kia Bazargan. 598-603 [doi]
- Global resource sharing for synthesis of control data flow graphs on FPGAsSeda Ogrenci Memik, Gokhan Memik, Roozbeh Jafari, Eren Kursun. 604-609 [doi]
- Compiler-generated communication for pipelined FPGA applicationsHeidi E. Ziegler, Mary W. Hall, Pedro C. Diniz. 610-615 [doi]
- Data communication estimation and reduction for reconfigurable systemsAdam Kaplan, Philip Brisk, Ryan Kastner. 616-621 [doi]
- Clock-tree power optimization based on RTL clock-gatingMonica Donno, Alessandro Ivaldi, Luca Benini, Enrico Macii. 622-627 [doi]
- Low-power design methodology for an on-chip bus with adaptive bandwidth capabilityRizwan Bashirullah, Wentai Liu, Ralph K. Cavin III. 628-633 [doi]
- Power-aware issue queue design for speculative instructionsTali Moreshet, R. Iris Bahar. 634-637 [doi]
- State-based power analysis for systems-on-chipReinaldo A. Bergamaschi, Yunjian Jiang. 638-641 [doi]
- Libraries: lifejacket or straitjacketCarl Sechen, Barbara Chappel, Jim Hogan, Andrew Moore, Tadahiko Nakamura, Gregory A. Northrop, Anjaneya Thakar. 642-643 [doi]
- Switch-level emulationAli Reza Ejlali, Seyed Ghassem Miremadi. 644-649 [doi]
- Designing fault tolerant systems into SRAM-based FPGAsFernanda Lima, Luigi Carro, Ricardo Augusto da Luz Reis. 650-655 [doi]
- Determining appropriate precisions for signals in fixed-point IIR filtersJoan Carletta, Robert J. Veillette, Frederick W. Krach, Zhengwei Fang. 656-661 [doi]
- Test generation for designs with multiple clocksXijiang Lin, Rob Thompson. 662-667 [doi]
- Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault modelsAngela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, T. M. Mak. 668-673 [doi]
- Using embedded infrastructure IP for SOC post-silicon verificationYu Huang, Wu-Tung Cheng. 674-677 [doi]
- Using satisfiability in application-dependent testing of FPGA interconnectsMehdi Baradaran Tahoori. 678-681 [doi]
- Design of a 10GHz clock distribution network using coupled standing-wave oscillatorsFrank O Mahony, C. Patrick Yue, Mark Horowitz, S. Simon Wong. 682-687 [doi]
- Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLLJohn G. Maneatis, Jaeha Kim, Iain McClatchie, Jay Maxey, Manjusha Shankaradas. 688-690 [doi]
- A reconfigurable signal processing IC with embedded FPGA and multi-port flash memoryMichele Borgatti, L. Cali, Guido De Sandre, B. Forét, D. Iezzi, Francesco Lertora, G. Muzzi, Marco Pasotti, Marco Poles, Pier Luigi Rolandi. 691-695 [doi]
- Physical synthesis methodology for high performance microprocessorsYiu-Hing Chan, Prabhakar Kudva, Lisa B. Lacey, Gregory A. Northrop, Thomas E. Rosser. 696-701 [doi]
- A 1.3GHz fifth generation SPARC64 microprocessorHisashige Ando, Yuuji Yoshida, Aiichiro Inoue, Itsumi Sugiyama, Takeo Asakawa, Kuniki Morita, Toshiyuki Muta, Tsuyoshi Motokurumada, Seishi Okada, Hideo Yamashita, Yoshihiko Satsukawa, Akihiko Konmoto, Ryouichi Yamashita, Hiroyuki Sugiyama. 702-705 [doi]
- A 1.5GHz third generation itanium® 2 processorJason Stinson, Stefan Rusu. 706-709 [doi]
- Formal verification - prove it or pitch itRajesh K. Gupta, Shishpal Rawat, Sandeep K. Shukla, Brian Bailey, Daniel K. Beece, Masahiro Fujita, Carl Pixley, John O Leary, Fabio Somenzi. 710-711 [doi]
- Algorithms in FastImp: a fast and wideband impedance extraction program for complicated 3-D geometriesZhenhai Zhu, Ben Song, Jacob White. 712-717 [doi]
- Vector potential equivalent circuit based on PEEC inversionHao Yu, Lei He. 718-723 [doi]
- On-chip interconnect-aware design and modeling methodology, based on high bandwidth transmission line devicesDavid Goren, Michael Zelikson, Rachel Gordin, Israel A. Wagner, Anastasia Barger, Alon Amir, Betty Livshitz, Anatoly Sherman, Youri Tretiakov, Robert A. Groves, J. Park, Donald L. Jordan, Sue E. Strang, Raminderpal Singh, Carl E. Dickey, David L. Harame. 724-727 [doi]
- An adaptive window-based susceptance extraction and its efficient implementationGuoan Zhong, Cheng-Kok Koh, Venkataramanan Balakrishnan, Kaushik Roy. 728-731 [doi]
- Test application time and volume compression through seed overlappingWenjing Rao, Ismet Bayraktaroglu, Alex Orailoglu. 732-737 [doi]
- Test cost reduction for SOCs using virtual TAMs and lagrange multipliersAnuja Sehgal, Vikram Iyengar, Mark D. Krasniewski, Krishnendu Chakrabarty. 738-743 [doi]
- A cost-effective scan architecture for scan testing with non-scan test power and test application costDong Xiang, Shan Gu, Jia-Guang Sun, Yu-Liang Wu. 744-747 [doi]
- On test data compression and n-detection test setsIrith Pomeranz, Sudhakar M. Reddy. 748-751 [doi]
- A retargetable micro-architecture simulatorWai Sum Mong, Jianwen Zhu. 752-757 [doi]
- Instruction set compiled simulation: a technique for fast and flexible instruction set simulationMehrdad Reshadi, Prabhat Mishra, Nikil D. Dutt. 758-763 [doi]
- Automated synthesis of efficient binary decoders for retargetable software toolkitsWei Qin, Sharad Malik. 764-769 [doi]
- Designing mega-ASICs in nanogate technologiesDavid E. Lackey, Paul S. Zuchowski, Jürgen Koehl. 770-775 [doi]
- Architecting ASIC libraries and flows in nanometer eraClive Bittlestone, Anthony M. Hill, Vipul Singhal, N. V. Arvind. 776-781 [doi]
- Exploring regular fabrics to optimize the performance-cost trade-offLawrence T. Pileggi, Herman Schmit, Andrzej J. Strojwas, Padmini Gopalakrishnan, V. Kheterpal, Aneesh Koorapaty, Chetan Patel, V. Rovner, K. Y. Tong. 782-787 [doi]
- Pushing ASIC performance in a power envelopeRuchir Puri, Leon Stok, John M. Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni. 788-793 [doi]
- An algebraic multigrid solver for analytical placement with layout based clusteringHongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu. 794-799 [doi]
- Wire length prediction based clustering and its application in placementBo Hu, Malgorzata Marek-Sadowska. 800-805 [doi]
- Dynamic global buffer planning optimization based on detail block locating and congestion analysisYuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu. 806-811 [doi]
- Multilevel floorplanning/placement for large-scale modules using B*-treesHsun-Cheng Lee, Yao-Wen Chang, Jer-Ming Hsu, Hannah Honghua Yang. 812-817 [doi]
- Checking satisfiability of a conjunction of BDDsRobert F. Damiano, James H. Kukula. 818-823 [doi]
- Learning from BDDs in SAT-based bounded model checkingAarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar. 824-829 [doi]
- A fast pseudo-boolean constraint solverDonald Chai, Andreas Kuehlmann. 830-835 [doi]
- Shatter: efficient symmetry-breaking for boolean satisfiabilityFadi A. Aloul, Igor L. Markov, Karem A. Sakallah. 836-839 [doi]
- SAT-based unbounded symbolic model checkingHyeong-Ju Kang, In-Cheol Park. 840-843 [doi]
- Design of a 17-million gate network processor using a design factoryGilles-Eric Descamps, Satish Bagalkotkar, Subramaniam Ganesan, Satish Iyengar, Alain Pirson. 844-849 [doi]
- Hybrid hierarchical timing closure methodology for a high performance and low power DSPKaijian Shi, Graig Godwin. 850-855 [doi]
- Statistical estimation of leakage-induced power grid voltage drop considering within-die process variationsImad A. Ferzli, Farid N. Najm. 856-859 [doi]
- Temporofunctional crosstalk noise analysisDonald Chai, Alex Kondratyev, Yajun Ran, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska. 860-863 [doi]
- Static noise analysis with noise windowsKen Tseng, Vinod Kariat. 864-868 [doi]
- Embedded intelligent SRAMPrabhat Jain, G. Edward Suh, Srinivas Devadas. 869-874 [doi]
- Improved indexing for cache miss reduction in embedded systemsTony Givargis. 875-880 [doi]
- Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system designYoonseo Choi, Taewhan Kim. 881-886 [doi]
- Interprocedural optimizations for improving data cache performance of array-intensive embedded applicationsWei Zhang 0002, Guangyu Chen, Mahmut T. Kandemir, Mustafa Karaköy. 887-892 [doi]
- Tutorial: basic concepts in quantum circuitsJohn P. Hayes. 893 [doi]
- Designing and implementing small quantum circuits and algorithmsBen Travaglione. 894-899 [doi]
- A survey of techniques for energy efficient on-chip communicationVijay Raghunathan, Mani B. Srivastava, Rajesh K. Gupta. 900-905 [doi]
- Extending the lifetime of a network of battery-powered mobile devices by remote processing: a markovian decision-based approachPeng Rong, Massoud Pedram. 906-911 [doi]
- Energy-aware MPEG-4 FGS streamingKihwan Choi, Kwanho Kim, Massoud Pedram. 912-915 [doi]
- A low-energy chip-set for wireless intercomM. Josie Ammer, Michael Sheets, Tufan C. Karalar, Mika Kuulusa, Jan M. Rabaey. 916-919 [doi]
- Optimal integer delay budgeting on directed acyclic graphsElaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh. 920-925 [doi]
- Optimizations for a simulator construction system supporting reusable componentsDavid A. Penry, David I. August. 926-931 [doi]
- Statistical timing for parametric yield prediction of digital integrated circuitsJochen A. G. Jess, K. Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah. 932-937 [doi]
- Interconnect and noise immunity design for the Pentium 4 processorRajesh Kumar. 938-943 [doi]
- Crosstalk noise in FPGAsYajun Ran, Malgorzata Marek-Sadowska. 944-949 [doi]
- Simple metrics for slew rate of RC circuits based on two circuit momentsKanak Agarwal, Dennis Sylvester, David Blaauw. 950-953 [doi]
- Post-route gate sizing for crosstalk noise reductionMurat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj. 954-957 [doi]
- Performance trade-off analysis of analog circuits by normal-boundary intersectionGuido Stehr, Helmut E. Graeb, Kurt Antreich. 958-963 [doi]
- Support vector machines for analog circuit performance representationFernando De Bernardinis, Michael I. Jordan, Alberto L. Sangiovanni-Vincentelli. 964-969 [doi]
- Efficient description of the design space of analog circuitsMaria del Mar Hershenson. 970-973 [doi]
- Architectural selection of A/D convertersMartin Vogels, Georges G. E. Gielen. 974-977 [doi]