Hyeong-Ju Kang - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 21 from 21

2023

AoCStream: All-on-Chip CNN Accelerator with Stream-Based Line-Buffer Architecture and Accelerator-Aware PruningHyeong-Ju Kang, Byung-Do Yang. sensors, 23(19):8104, October 2023. [doi]

AoCStream: All-on-Chip CNN Accelerator With Stream-Based Line-Buffer ArchitectureHyeong-Ju Kang. fpga 2023: 48 [doi]

2020

Accelerator-Aware Pruning for Convolutional Neural NetworksHyeong-Ju Kang. tcsv, 30(7):2093-2103, 2020. [doi]

Low-Area and Low-Power Latch-Based Thermometer-Code Shift-RegisterKi-Chan Woo, Hyeong-Ju Kang, Byung-Do Yang. tcas, 67-II(10):2119-2123, 2020. [doi]

2019

Short floating-point representation for convolutional neural network inferenceHyeong-Ju Kang. ieiceee, 16(2):20180909, 2019. [doi]

Real-Time Object Detection on 640x480 Image With VGG16+SSDHyeong-Ju Kang. icfpt 2019: 419-422 [doi]

Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-LatchesKi-Chan Woo, Hyeong-Ju Kang, Byung-Do Yang. tcas, 66-II(8):1386-1390, 2019. [doi]

2013

Area-efficient convolutional deinterleaver for mobile TV receiverHyeong-Ju Kang, Hee Suk Seo, Jin Kwak. tecs, 12(2):28, 2013. [doi]

2012

Low-Power Time Deinterleaver for ISDB-T ReceiverHyeong-Ju Kang, Byung-Do Yang. tcas, 59-II(10):668-672, 2012. [doi]

2011

Area-Efficient Prefilter Architecture for a CDMA ReceiverHyeong-Ju Kang, Seung Jae Lee, Byung-Do Yang. tcas, 58-II(4):220-224, 2011. [doi]

A Low Power Content Addressable Memory Using Low Swing Search LinesByung-Do Yang, Yong Kyu Lee, Si-Woo Sung, Jae-Joong Min, Jae-Mun Oh, Hyeong-Ju Kang. tcas, 58-I(12):2849-2858, 2011. [doi]

2005

SAT-based unbounded symbolic model checkingHyeong-Ju Kang, In-Cheol Park. tcad, 24(2):129-140, 2005. [doi]

A scalable SIMD digital signal processor for high-quality multifunctional printer systemsHyeong-Ju Kang, Yongwoo Choi, Kimo Kim, In-Cheol Park, Jung-Wook Kim, Eul-Hwan Lee, Goo-Soo Gahang. clrimg 2005: 448-456 [doi]

2003

Pairing and ordering to reduce hardware complexity in cascade form filter designHyeong-Ju Kang, In-Cheol Park. iscas 2003: 265-268 [doi]

SAT-based unbounded symbolic model checkingHyeong-Ju Kang, In-Cheol Park. dac 2003: 840-843 [doi]

A 24-bit floating-point audio DSP controller supporting fast exponentiationSung-Won Lee, Hyeong-Ju Kang, In-Cheol Park. iscas 2003: 748-751 [doi]

2002

A high-speed and low-latency Reed-Solomon decoder based on a dual-line structureHyeong-Ju Kang, In-Cheol Park. icassp 2002: 3180-3183 [doi]

Digital filter synthesis based on an algorithm to generate all minimal signed digit representationsIn-Cheol Park, Hyeong-Ju Kang. tcad, 21(12):1525-1529, 2002. [doi]

2001

Multiplier-less IIR filter synthesis algorithms to trade-off the delay and the number of addersHyeong-Ju Kang, In-Cheol Park. iscas 2001: 693-696 [doi]

Digital Filter Synthesis Based on Minimal Signed Digit RepresentationIn-Cheol Park, Hyeong-Ju Kang. dac 2001: 468-473 [doi]

2000

FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of AddersHyeong-Ju Kang, Hansoo Kim, In-Cheol Park. iccad 2000: 51-54

Sign in or sign up to see more results.

runs on WebDSL