Abstract is missing.
- Physical Planning with RetimingJason Cong, Sung Kyu Lim. 2-7
- Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing FloorplanXianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, Jun Gu. 8-12
- Modeling Non-Slicing Floorplans with Binary TreesFlorin Balasa. 13-16
- On Mismatches between Incremental Optimizers and Instance Perturbations in Physical Design ToolsAndrew B. Kahng, Stefanus Mantik. 17-21
- Event Driven Simulation Without Loops or ConditionalsPeter M. Maurer. 23-26
- Observability Analysis of Embedded Software for Coverage-Directed ValidationJosé C. Costa, Srinivas Devadas, José Monteiro. 27-32
- A Methodology for Verifying Memory Access Protocols in Behavioral SynthesisGernot Koch, Taewhan Kim, Reiner Genevriere. 33-38
- Symbolic Debugging Scheme for Optimized Hardware and SoftwareFarinaz Koushanfar, Darko Kirovski, Miodrag Potkonjak. 40-43
- Automated Data Dependency Size Estimation with a Partially Fixed Execution OrderingPer Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas. 44-50
- FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of AddersHyeong-Ju Kang, Hansoo Kim, In-Cheol Park. 51-54
- Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron DesignYu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu, Dirk Stroobandt, Dennis Sylvester. 56-61
- Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital CircuitsMichael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu. 62-67
- Miller Factor for Gate-Level Coupling Delay CalculationPinhong Chen, Desmond Kirkpatrick, Kurt Keutzer. 68-74
- Challenges and Opportunities in Broadband and Wireless Communication DesignsJan M. Rabaey, Miodrag Potkonjak, Farinaz Koushanfar, Suet-Fei Li, Tim Tuan. 76-82
- Challenges in Physical Chip DesignRalph H. J. M. Otten, Paul Stravers. 84-91
- General Models for Optimum Arbitrary-Dimension FPGA Switch Box DesignsHongbing Fan, Jiping Liu, Yu-Liang Wu. 93-98
- A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple NetsJiang Hu, Sachin S. Sapatnekar. 99-103
- Provably Good Global Buffering Using an Available Buffer Block PlanFeodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky. 104-109
- Predictable RoutingRyan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh. 110-113
- Counterexample-Guided Choice of Projections in Approximate Symbolic Model CheckingShankar G. Govindaraju, David L. Dill. 115-119
- Smart Simulation Using Collaborative Formal and Simulation EnginesPei-Hsin Ho, Thomas R. Shiple, Kevin Harer, James H. Kukula, Robert F. Damiano, Valeria Bertacco, Jerry Taylor, Jiang Long. 120-126
- Simulation Coverage Enhancement Using Test Stimulus TransformationsC. Norris Ip. 127-133
- Dynamic Response Time Optimization for SDF GraphsDirk Ziegenbein, Jan Uerpmann, Ralph Ernst. 135-140
- Full-Chip, Three-Dimensional, Shapes-Based RLC ExtractionKenneth L. Shepard, Dipak Sitaram, Yu Zheng. 142-149
- How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element KAnirudh Devgan, Hao Ji, Wayne Wei-Ming Dai. 150-155
- Generalized FDTD-ADI: An Unconditionally Stable Full-Wave Maxwell s Equations Solver for VLSI Interconnect ModelingCharlie Chung-Ping Chen, Tae-Woo Lee, Narayanan Murugesan, Susan C. Hagness. 156-163
- MONGREL: Hybrid Techniques for Standard Cell PlacementSung-Woo Hur, John Lillis. 165-170
- Multilevel Optimization for Large-Scale Circuit PlacementTony F. Chan, Jason Cong, Tianming Kong, Joseph R. Shinnerl. 171-176
- A Force-Directed Macro-Cell PlacerFan Mo, Abdallah Tabbara, Robert K. Brayton. 177-180
- Verification of Delta-Sigma Converters Using Adaptive Regression ModelingJeongjin Roh, Suresh Seshadri, Jacob A. Abraham. 182-187
- DAISY: A Simulation-Based High-Level Synthesis Tool for Delta-Sigma ModulatorsKenneth Francken, Peter J. Vancorenland, Georges G. E. Gielen. 188-192
- ACTIF: A High-Level Power Estimation Tool for Analog Continuous-Time-FiltersErik Lauwers, Georges G. E. Gielen. 193-196
- Potential Slack: An Effective Metric of Combinational Circuit PerformanceChunhong Chen, Xiaojian Yang, Majid Sarrafzadeh. 198-201
- Delay Budgeting for a Timing-Closure-Driven Design MethodChien-Chu Kuo, Allen C.-H. Wu. 202-207
- Stochastic Wire-Length and Delay Distribution of 3-Dimensional CircuitsRongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes. 208-213
- Hierarchical Interconnect Circuit ModelsMichael W. Beattie, Satrajit Gupta, Lawrence T. Pileggi. 215-221
- Hurwitz Stable Reduced Order Modelling for RLC Interconnect TreesXiaodong Yang, Chung-Kuan Cheng, Walter H. Ku, Robert J. Carragher. 222-228
- An Effective Capacitance Based Delay Metric for RC InterconnectChandramouli V. Kashyap, Charles J. Alpert, Anirudh Devgan. 229-234
- Incremental CADOlivier Coudert, Jason Cong, Sharad Malik, Majid Sarrafzadeh. 236-243
- Decomposing Refinement Proofs Using Assume-Guarantee ReasoningThomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani. 245-252
- Effective Partition-Driven Placement with Simultaneous Level Processing and a Global Net ViewsKe Zhong, Shantanu Dutt. 254-259
- DRAGON2000: Standard-Cell Placement Tool for Large Industry CircuitsMaogang Wang, Xiaojian Yang, Majid Sarrafzadeh. 260-263
- Data Path Placement with RegularityTerry Tao Ye, Giovanni De Micheli. 264-270
- Efficient Finite-Difference Method for Quasi-Periodic Steady-State and Small Signal AnalysesBaolin Yang, Dan Feng. 272-276
- Noise Analysis of Phase-Locked LoopsAmit Mehrotra. 277-282
- Computing Phase Noise Eigenfunctions Directly from Steady-State Jacobian MatricesAlper Demir, David E. Long, Jaijeet S. Roychowdhury. 283-288
- Modelling and Analysis of Communication Circuit Performance Using Markov Chains and Efficient Graph RepresentationsAlper Demir, Peter Feldmann. 290-295
- Pipeline Optimization for Asynchronous Circuits: Complexity Analysis and an Efficient Optimal AlgorithmSangyun Kim, Peter A. Beerel. 296-302
- Achieving Fast and Exact Hazard-Free Logic Minimization of Extended Burst-Mode gC Finite State MachinesHans M. Jacobson, Chris J. Myers, Ganesh Gopalakrishnan. 303-310
- Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow MethodSungpack Hong, Taewhan Kim. 312-317
- Coupling-Driven Signal Encoding Scheme for Low-Power Interface DesignKi-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. Liu, Sung-Mo Kang. 318-321
- Bus Energy Minimization by Transition Pattern Coding (TPC) in Deep Submicron TechnologiesPaul-Peter Sotiriadis, Anantha Chandrakasan. 322-327
- Why Doesn t EDA Get Enough Respect?Andreas Bechtolsheim, Joe Costello, Aart de Gues, Patrick Scaglia, Jennifer Smith. 329
- Switching Window Computation for Static Timing Analysis in Presence of Crosstalk NoisePinhong Chen, Desmond Kirkpatrick, Kurt Keutzer. 331-337
- Slope Propagation in Static Timing AnalysisDavid Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda. 338-343
- Transistor-Level Timing Analysis Using Embedded SimulationPawan Kulshreshtha, Robert Palermo, Mohammad Mortazavi, Cyrus Bamji, Hakan Yalcin. 344-348
- Latency Effects of System Level Power Management AlgorithmsDinesh Ramanathan, Sandy Irani, Rajesh K. Gupta. 350-356
- Power-Conscious Joint Scheduling of Periodic Task Graphs and Aperiodic Tasks in Distributed Real-Time Embedded SystemsJiong Luo, Niraj K. Jha. 357-364
- Power Optimization of Real-Time Embedded Systems on Variable Speed ProcessorsYoungsoo Shin, Kiyoung Choi, Takayasu Sakurai. 365-368
- A Data Flow Fault Coverage Metric for Validation of Behavioral HDL DescriptionsQiushuang Zhang, Ian G. Harris. 369-372
- Simultaneous Gate Sizing and Fanout OptimizationWei Chen, Cheng-Ta Hsieh, Massoud Pedram. 374-378
- Layout-Driven Area-Constrained Timing Optimization by Net BufferingRajeev Murgai. 379-386
- Synthesis of CMOS Domino Circuits for Charge Sharing AlleviationChing-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen-Ben Jone, Jinn-Shyan Wang. 387-390
- Test of Future System-on-ChipsYervant Zorian, Sujit Dey, Mike Rodgers. 392-398
- UST/DME: A Clock Tree Router for General Skew ConstraintsChung-Wen Albert Tsao, Cheng-Kok Koh. 400-405
- A Twisted Bundle Layout Structure for Minimizing Inductive Coupling NoiseGuoan Zhong, Cheng-Kok Koh, Kaushik Roy. 406-411
- Cross-Talk Immune VLSI Design Using a Network of PLAs Embedded in a Regular Layout FabricSunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 412-418
- Latency-Guided On-Chip Bus Network DesignMilenko Drinic, Darko Kirovski, Seapahn Meguerdichian, Miodrag Potkonjak. 420-423
- Efficient Exploration of the SoC Communication Architecture Design SpaceKanishka Lahiri, Anand Raghunathan, Sujit Dey. 424-430
- MIST: An Algorithm for Memory Miss Traffic ManagementPeter Grun, Nikil D. Dutt, Alexandru Nicolau. 431-437
- Regularity Driven Logic SynthesisThomas Kutzschebauch, Leon Stok. 439-446
- Timing Driven Gate Duplication: Complexity Issues and AlgorithmsAnkur Srivastava, Ryan Kastner, Majid Sarrafzadeh. 447-450
- An Exact Gate Assignment Algorithm for Tree Circuits Under Rise and Fall DelaysArlindo L. Oliveira, Rajeev Murgai. 451-457
- Improving the Proportion of At-Speed Tests in Scan BISTYu Huang, Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski. 459-463
- Fast Test Application Technique Without Fast Scan ClocksSeonki Kim, Bapiraju Vinnakota. 464-467
- Error Catch and Analysis for Semiconductor Memories Using March TestsChi-Feng Wu, Chih-Tsun Huang, Chih-Wea Wang, Kuo-Liang Cheng, Cheng-Wen Wu. 468-471
- Diagnosis of Interconnect Faults in Cluster-Based FPGA ArchitecturesIan G. Harris, Russell Tessier. 472-475
- Fast Analysis and Optimization of Power/Ground NetworksHaihua Su, Kaushik Gala, Sachin S. Sapatnekar. 477-480
- Simulation and Optimization of the Power Distribution Network in VLSI CircuitsGeng Bai, Sudhakar Bobba, Ibrahim N. Hajj. 481-486
- Frequency Domain Analysis of Switching Noise on Power Supply NetworkShiyou Zhao, Kaushik Roy, Cheng-Kok Koh. 487-492
- Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise EffectsJing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng. 493-496
- Power Exploration for Embedded VLIW ArchitecturesMariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria. 498-503
- Exploring Performance Tradeoffs for Clustered VLIW ASIPsMargarida F. Jacome, Gustavo de Veciana, Viktor S. Lapinskii. 504-510
- Synthesis of Operation-Centric Hardware DescriptionsJames C. Hoe, Arvind. 511-518
- Don t Cares and Multi-Valued Logic Network MinimizationYunjian Jiang, Robert K. Brayton. 520-525
- Generalized Symmetries in Boolean FunctionsVictor N. Kravets, Karem A. Sakallah. 526-532
- Wire Reconnections Based on Implication Flow GraphShih-Chieh Chang, Zhong-Zhen Wu, He-Zhe Yu. 533-536
- Deterministic Test Pattern Generation Techniques for Sequential CircuitsIlker Hamzaoglu, Janak H. Patel. 538-543
- Simulation Based Test Generation for Scan DesignsIrith Pomeranz, Sudhakar M. Reddy. 544-549
- Test Generation for Acyclic Sequential Circuits with Hold RegistersTomoo Inoue, Debesh Kumar Das, Chiiho Sano, Takahiro Mihara, Hideo Fujiwara. 550-556
- A Parametric Test Method for Analog Components in Integrated Mixed-Signal CircuitsMichael Pronath, Volker Gloeckel, Helmut E. Graeb. 557-561
- Partial Simulation-Driven ATPG for Detection and Diagnosis of Faults in Analog CircuitsSudip Chakrabarti, Abhijit Chatterjee. 562-567
- System and Architecture-Level Power Reduction for Microprocessor-Based Communication and Multi-Media ApplicationsLode Nachtergaele, Vivek Tiwari, Nikil D. Dutt. 569-573
- Design-Manufacturing Interface for 0.13 Micron and BelowAndrzej J. Strojwas. 575