Linda Milor - researchr alias

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Viewing Publication 1 - 53 from 53

2022

CacheEM: For Reliability Analysis on Cache Memory Aging Due to ElectromigrationRui Zhang 0048, Taizhi Liu, Kexin Yang 0001, Linda Milor. tcad, 41(9):3078-3091, 2022. [doi]

2021

A Comprehensive Framework for Analysis of Time-Dependent Performance-Reliability Degradation of SRAM Cache MemoryRui Zhang 0048, Kexin Yang, Zhaocheng Liu, Taizhi Liu, Wenshan Cai, Linda Milor. tvlsi, 29(5):857-870, 2021. [doi]

2020

2019

2018

Comprehensive Reliability-Aware Statistical Timing Analysis Using a Unified Gate-Delay Model for MicroprocessorsTaizhi Liu, Chang-Chih Chen, Linda Milor. tetc, 6(2):219-232, 2018. [doi]

Optimal Accelerated Test Regions for Time- Dependent Dielectric Breakdown Lifetime Parameters Estimation in FinFET TechnologyKexin Yang, Rui Zhang, Taizhi Liu, Dae-Hyun Kim, Linda Milor. dcis 2018: 1-6 [doi]

Circuit-level reliability simulator for front-end-of-line and middle-of-line time-dependent dielectric breakdown in FinFET technologyKexin Yang, Taizhi Liu, Rui Zhang, Linda Milor. vts 2018: 1-6 [doi]

A Comprehensive Time-Dependent Dielectric Breakdown Lifetime Simulator for Both Traditional CMOS and FinFET TechnologyKexin Yang, Taizhi Liu, Rui Zhang, Linda Milor. tvlsi, 26(11):2470-2482, 2018. [doi]

Estimation of the Optimal Accelerated Test Region for FinFET SRAMs Degraded by Front-End and Back-End Wearout MechanismsRui Zhang, Kexin Yang, Taizhi Liu, Linda Milor. dcis 2018: 1-6 [doi]

2017

Negative Bias Temperature Instability and Gate Oxide Breakdown Modeling in Circuits With Die-to-Die Calibration Through Power Supply and Ground Signal MeasurementsSoonyoung Cha, Taizhi Liu, Linda Milor. tvlsi, 25(8):2271-2284, 2017. [doi]

Adaptive supply voltage and duty cycle controller for yield-power optimization of ICsSoonyoung Cha, Linda Milor. iwasi 2017: 133-138 [doi]

On-line monitoring of system health using on-chip SRAMs as a wearout sensorWoongrae Kim, Taizhi Liu, Linda Milor. iolts 2017: 253-258 [doi]

A methodology for estimating memory lifetime using a system-level accelerated life test and error-correcting codesDae-Hyun Kim, Linda Milor. vts 2017: 1-6 [doi]

Analysis of errors in estimating wearout characteristics of time-dependent dielectric breakdown using system-level accelerated life testDae-Hyun Kim, Linda Milor. mr, 76:47-52, 2017. [doi]

An ECC-Assisted Postpackage Repair Methodology in Main Memory SystemsDae-Hyun Kim, Linda Milor. tvlsi, 25(7):2045-2058, 2017. [doi]

Front-end of line and middle-of-line time-dependent dielectric breakdown reliability simulator for logic circuitsKexin Yang, Taizhi Liu, Rui Zhang, Dae-Hyun Kim, Linda Milor. mr, 76:81-86, 2017. [doi]

Analysis of time-dependent dielectric breakdown induced aging of SRAM cache with different configurationsRui Zhang, Taizhi Liu, Kexin Yang, Linda Milor. mr, 76:87-91, 2017. [doi]

2016

System-Level Modeling of Microprocessor Reliability Degradation Due to Bias Temperature Instability and Hot Carrier InjectionChang-Chih Chen, Taizhi Liu, Linda Milor. tvlsi, 24(8):2712-2725, 2016. [doi]

Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory ArrayWoongrae Kim, Chang-Chih Chen, Dae-Hyun Kim, Linda Milor. tvlsi, 24(7):2521-2534, 2016. [doi]

2015

MBIST and statistical hypothesis test for time dependent dielectric breakdowns due to GOBD vs. BTDDB in an SRAM arrayWoongrae Kim, Chang-Chih Chen, Soonyoung Cha, Linda Milor. vts 2015: 1-6 [doi]

Estimation of remaining life using embedded SRAM for wearout parameter extractionWoongrae Kim, Chang-Chih Chen, Taizhi Liu, Soonyoung Cha, Linda Milor. iwasi 2015: 243-248 [doi]

System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdownTaizhi Liu, Chang-Chih Chen, Soonyoung Cha, Linda Milor. mr, 55(9-10):1334-1340, 2015. [doi]

Comprehensive reliability and aging analysis on SRAMs within microprocessor systemsTaizhi Liu, Chang-Chih Chen, Woongrae Kim, Linda Milor. mr, 55(9-10):1290-1296, 2015. [doi]

Panel: Analog/RF BIST: Are we there yet?Sule Ozev, Linda Milor. vts 2015: 1 [doi]

2014

Backend Dielectric Reliability Full Chip SimulatorMuhammad Muqarrab Bashir, Chang-Chih Chen, Linda Milor, Dae-Hyun Kim, Sung Kyu Lim. tvlsi, 22(8):1750-1762, 2014. [doi]

Built-in self test methodology for diagnosis of backend wearout mechanisms in SRAM cellsWoongrae Kim, Linda Milor. vts 2014: 1-6 [doi]

2013

2012

2011

Impact of irregular geometries on low-k dielectric breakdownMuhammad Bashir, Linda Milor, Dae-Hyun Kim, Sung Kyu Lim. mr, 51(9-11):1582-1586, 2011. [doi]

2010

Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BISTFahad Ahmed, Linda Milor. vts 2010: 63-68 [doi]

Via wearout detection with on-chip monitorsFahad Ahmed, Linda Milor. mj, 41(11):789-800, 2010. [doi]

2009

Modeling Low-k Dielectric Breakdown to Determine Lifetime RequirementsMuhammad Bashir, Linda Milor. dt, 26(6):18-27, 2009. [doi]

A DLL Design for Testing I/O Setup and Hold TimesCheng Jia, Linda Milor. tvlsi, 17(11):1579-1592, 2009. [doi]

2007

Modeling of the breakdown mechanisms for porous copper/low-k process flowsChangsoo Hong, Linda Milor. mr, 47(9-11):1478-1482, 2007. [doi]

Backend dielectric breakdown dependence on linewidth and pattern densityLinda Milor, Changsoo Hong. mr, 47(9-11):1473-1477, 2007. [doi]

2004

Analysis of the layout impact on electric fields in interconnect structures using finite element methodChangsoo Hong, Linda Milor, M. Z. Lin. mr, 44(9-11):1867-1871, 2004. [doi]

2002

Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuitsMichael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu. tcad, 21(5):544-553, 2002. [doi]

2000

Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital CircuitsMichael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu. iccad 2000: 62-67

1990

Computing Parametric Yield Accurately and EfficientlyLinda Milor, Alberto L. Sangiovanni-Vincentelli. iccad 1990: 116-119

Optimal Test Set Design for Analog CircuitsLinda Milor, Alberto L. Sangiovanni-Vincentelli. iccad 1990: 294-297

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2016

2015

2014

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2010

2009

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1990

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