Abstract is missing.
- A cost-efficient dependability management framework for self-aware system-on-chips based on IEEE 1687Ahmed Ibrahim, Hans G. Kerkhoff. 1-2 [doi]
- A new 3-bit burst-error correcting codeA. Klockmann, Georg Georgakos, Michael Gössel. 3-4 [doi]
- SICTA: A superimposed in-circuit fault tolerant architecture for SRAM-based FPGAsAlexandra Kourfali, Amit Kulkarni 0002, Dirk Stroobandt. 5-8 [doi]
- Assessment of the amplitude-duration criterion for SET/SEU robustness evaluationMarko Andjelkovic, Milos Krstic, Rolf Kraemer. 9-12 [doi]
- Automating wafer-level test of uncooled infrared detectors using wafer-proberMohamed Makhlouf, Diana Goller, Lutz Gendrisch, Stephan Kolnsberg, Franz Vogt, Alexander Utz, Dirk Weiler, Holger Vogt. 13-16 [doi]
- Controller augmentation and test point insertion at RTL for concurrent operational unit testingToshinori Hosokawa, Shun Takeda, Hiroshi Yamazaki, Masayoshi Yoshimura. 17-20 [doi]
- Deterministic network on chip for deploying real time applications on many-core processorsStefano Esposito, Massimo Violante. 21-24 [doi]
- Diagnosis with transition faults on embedded segmentsTheodoros Toulas, Spyros Tragoudas. 25-27 [doi]
- BPPT - Bulk potential protection technique for hardened sequentialsI. Nofal, Adrian Evans, A.-L. He, Gang Guo, Yuanqing Li, Li Chen, Rui Liu, H. B. Wang, Mo Chen, S. H. Baeg, Shi-Jie Wen, Richard Wong. 28-32 [doi]
- Comprehensive analysis of sequential circuits vulnerability to transient faults using SMTGhaith Bany Hamad, Ghaith Kazma, Otmane Aït Mohamed, Yvon Savaria. 33-38 [doi]
- Design-time reliability evaluation for digital circuitsMohamed A. Abufalgha, Alex Bystrov. 39-44 [doi]
- Relaxing DRAM refresh rate through access pattern scheduling: A case study on stencil-based algorithmsKonstantinos Tovletoglou, Dimitrios S. Nikolopoulos, Georgios Karakonstantis. 45-50 [doi]
- Voltage margins identification on commercial x86-64 multicore microprocessorsGeorge Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, Charalampos Magdalinos, Dimitris Gizopoulos. 51-56 [doi]
- A generic embedded sequence generator for constrained-random validation with weighted distributionsXiaobing Shi, Nicola Nicolici. 57-62 [doi]
- An effective functional safety infrastructure for system-on-chipsChristophe Eychenne, Yervant Zorian. 63-66 [doi]
- On the in-field test of embedded memoriesPaolo Bernardi, Marco Restifo, E. Sanchez, Matteo Sonza Reorda. 67-70 [doi]
- Advanced ECC solution for automotive SoCsH. Shaheen, G. Boschi, Gurgen Harutyunyan, Yervant Zorian. 71-73 [doi]
- VPUF: Voter based physical unclonable function with high reliability and modeling attack resistanceJing Ye, Yu Hu, Xiaowei Li. 74-79 [doi]
- NBTI/PBTI tolerant arbiter PUF circuitsKoyo Suzuki, Katsuyoshi Miura, Koji Nakamae. 80-84 [doi]
- Thermal laser attack and high temperature heating on HfO2-based OxRAM cellsAlexis Krakovinsky, Marc Bocquet, Romain Wacquez, J. Coignus, Jean Michel Portal. 85-89 [doi]
- Reliability issues in RRAM ternary memories affected by variability and aging mechanismsAntonio Rubio, Manel Escudero, Peyman Pouyan. 90-92 [doi]
- 6T CMOS SRAMs reliability monitoring through stability measurementsBartomeu Alorda, Gabriel Torrens, Sebastiàn A. Bota. 93-95 [doi]
- In-situ Fmax/Vmin tracking for energy efficiency and reliability optimizationIvan Miro Panades, Edith Beigné, Olivier Billoint, Yvain Thonnart. 96-99 [doi]
- Variation tolerant BTI monitoring in SRAM cellsYiorgos Sfikas, Yiorgos Tsiatouhas. 100-105 [doi]
- Dynamic aging compensation and Safety measures in Automotive environmentSouhir Mhira, Vincent Huard, Ahmed Benhassain, Florian Cacho, Sylvie Naudet, A. Jain, C. R. Parthasarathy, Alain Bravaix. 106-112 [doi]
- Minimal exercise vector generation for reliability improvementP. Madhukar Reddy, Stavros Hadjitheophanous, Vassos Soteriou, Paul V. Gratz, Maria K. Michael. 113-119 [doi]
- An on-line test strategy and analysis for a 1T1R crossbar memoryManuel Escudero-Lopez, Francesc Moll, Antonio Rubio, Ioannis Vourkas. 120-125 [doi]
- Reliability analysis of MTJ-based functional module for neuromorphic computingElena Ioana Vatajelu, Lorena Anghel. 126-131 [doi]
- Revisiting random access scan for effective enhancement of post-silicon observabilityBinod Kumar 0001, Ankit Jindal, Jaynarayan T. Tudu, Brajesh Pandey, Virendra Singh. 132-137 [doi]
- SIFI: AMD southern islands GPU microarchitectural level fault injectorAlessandro Vallero, Dimitris Gizopoulos, Stefano Di Carlo. 138-144 [doi]
- EDA support for functional safety - How static and dynamic failure analysis can improve productivity in the assessment of functional safetyDan Alexandrescu, Adrian Evans, Maximilien Glorieux, Issam Nofal. 145-150 [doi]
- Simulation-based analysis of FF behavior in presence of power supply noiseYukiya Miura, Takuya Yamamoto. 151-156 [doi]
- Robustness in automotive electronics: An industrial overview of major concernsUlrich Backhausen, Oscar Bailan, Paolo Bemardi, Sergio de Luca, Julie Henzler, Thomas Kern, Davide Piumatti, Thomas Rabenalt, Krishnapriya Chakiat Ramamoorthy, Ernesto Sánchez, Alessandro Sansonetti, Rudolf Ullmann, Federico Venini, Robert Wiesner. 157-162 [doi]
- Cache timing attacks countermeasures and error detection in Euclidean addition chains based scalar multiplication algorithm for elliptic curvesFangan-Yssouf Dosso, Pascal Véron. 163-168 [doi]
- Jamming resistant encoding for non-uniformly distributed informationBatya Karp, Yerucham Berkowitz, Osnat Keren. 169-173 [doi]
- Analysis of radiation-induced cross domain errors in TMR architectures on SRAM-based FPGAsLuca Sterpone, Luca Boragno. 174-179 [doi]
- Field profiling & monitoring of payload transistors in FPGAsDa Cheng, Amitava Majumdar, Xiaobao Wang, Nui Chong. 180-185 [doi]
- PUFMon: Security monitoring of FPGAs using physically unclonable functionsShahin Tajik, Julian Fietkau, Heiko Lohrke, Jean-Pierre Seifert, Christian Boit. 186-191 [doi]
- Design of efficient error resilience in signal processing and control systems: From algorithms to circuitsJacob A. Abraham, Suvadeep Banerjee, Abhijit Chatterjee. 192-195 [doi]
- Reliability of computing systems: From flip flops to variablesGiorgio Di Natale, Maha Kooli, Alberto Bosio, Michele Portolan, Régis Leveugle. 196-198 [doi]
- On comparison of robust configurable FPGA encoders for dependable industrial communication systemsPetr Pfeifer, Farnoosh Hosseinzadeh, Heinrich Theodor Vierhaus. 199-200 [doi]
- On-line testing of sensor networks: A case studyJ. A. Miranda, Anna Vaskova, Marta Portela-García, Mario García-Valderas, Celia López-Ongil. 201-202 [doi]
- Handling of permanent faults in dynamically scheduled processorsFelix Mühlbauer, Lukas Schroder, Mario Schölzel. 203-204 [doi]
- Polymorphic PUF: Exploiting reconfigurability of CPU+FPGA SoC to resist modeling attackJing Ye, Yue Gong, Yu Hu, Xiaowei Li. 205-206 [doi]
- Soft error analysis of MTJ-based logic-in-memory full adder: Threats and solutionJavad Talafy, Hamid R. Zarandi. 207-208 [doi]
- Soft errors: Reliability challenges in energy-constrained ULP body sensor networks applicationsHarsh N. Patel, Benton H. Calhoun, Randy W. Mann. 209-210 [doi]
- Test pattern generation to detect multiple faults in ROBDD based combinational circuitsToral Shah, Anzhela Matrosova, Virendra Singh. 211-212 [doi]
- Trojan circuits preventing and masking in sequential circuitsAnjela Matrosova, Eugeniy Mitrofanov, Sergei Ostanin, Irina Kirienko. 213-214 [doi]
- Hardware Trojan detection and classification based on steady state learningMasaru Oya, Masao Yanagisawa, Nozomu Togawa. 215-220 [doi]
- Weighted logic locking: A new approach for IC piracy protectionNikolaos Karousos, Konstantinos Pexaras, Irene G. Karybali, Emmanouil Kalligeros. 221-226 [doi]
- Hardware Trojans classification for gate-level netlists using multi-layer neural networksKento Hasegawa, Masao Yanagisawa, Nozomu Togawa. 227-232 [doi]
- Design flows for resilient energy-efficient systemsMohammad Saber Golanbari, Mehdi Baradaran Tahoori. 233-236 [doi]
- Energy-efficient and error-resilient iterative solvers for approximate computingAlexander Scholl, Claus Braun, Hans-Joachim Wunderlich. 237-239 [doi]
- Temporal redundancy latch-based architecture for soft error mitigationRobert Schmidt, Alberto García Ortiz, Goerschwin Fey. 240-243 [doi]
- Reliable gas sensing with memristive arrayAdedotun Adeyemo, Abusaleh M. Jabir, Jimson Mathew, Eugenio Martinelli, Corrado Di Natale, Marco Ottavi. 244-246 [doi]
- Investigation of critical path selection for in-situ monitors insertionFlorian Cacho, Ahmed Benhassain, R. Shah, Souhir Mhira, Vincent Huard, Lorena Anghel. 247-252 [doi]
- On-line monitoring of system health using on-chip SRAMs as a wearout sensorWoongrae Kim, Taizhi Liu, Linda Milor. 253-258 [doi]
- Instruction-based self-test for delay faults maximizing operating temperatureNihar Hage, Rohini Gulve, Masahiro Fujita, Virendra Singh. 259-264 [doi]
- Fast power overhead prediction for hardware redundancy-based fault toleranceStefan Scharoba, Heinrich Theodor Vierhaus. 265-270 [doi]
- Probabilistic error detection and correction in switched capacitor circuits using checksum codesMd Imran Momtaz, Suvadeep Banerjee, Abhijit Chatterjee. 271-276 [doi]