Table of Contents

• Functional analysis of circuits under timing variationsMehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan. 1 [doi]
• Exact stuck-at fault classification in presence of unknownsStefan Hillebrecht, Michael A. Kochte, Hans-Joachim Wunderlich, Bernd Becker. 1-6 [doi]
• Fault tolerant FPGA processor based on runtime reconfigurable modulesMihalis Psarakis, Andreas Apostolakis. 1-6 [doi]
• Disturbance fault testing on various NAND flash memoriesChih-Sheng Hou, Jin-Fu Li. 1 [doi]
• Diagnostic system based on support-vector machines for board-level functional diagnosisZhaobo Zhang, Xinli Gu, Yaohui Xie, Zhiyuan Wang, Zhanglei Wang, Krishnendu Chakrabarty. 1-6 [doi]
• OBT for settling error test of sampled-data systems using signal-dependent clockingManuel J. Barragan Asian, Gildas Leger, José L. Huertas. 1-6 [doi]
• Cost and power efficient timing error tolerance in flip-flop based microprocessor coresStefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni. 1-6 [doi]
• Fault-Tolerant Algebraic Architecture for radiation induced soft-errorsFábio P. Itturriet, Ronaldo Rodrigues Ferreira, Luigi Carro. 1 [doi]
• DfT support for launch and capture power reduction in launch-off-capture testingSamah Mohamed Saeed, Ozgur Sinanoglu. 1-6 [doi]
• On the quality of test vectors for post-silicon characterizationMatthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian. 1-6 [doi]
• Functional test generation for hard to detect stuck-at faults using RTL model checkingMahesh Prabhu, Jacob A. Abraham. 1-6 [doi]
• Toggle-masking scheme for x-filteringAbishek Ramdas, Ozgur Sinanoglu. 1-6 [doi]
• Adaptive testing of chips with varying distributions of unknown response bitsChandra K. H. Suresh, Ozgur Sinanoglu, Sule Ozev. 1-6 [doi]
• Enhanced reduced code linearity test technique for multi-bit/stage pipeline ADCsAsma Laraba, Haralampos-G. D. Stratigopoulos, Salvador Mir, Herve Naudet, Christophe Forel. 1-6 [doi]
• The impact of functional safety standards in the design and test of reliable and available integrated circuitsRiccardo Mariani. 1 [doi]
• On-chip delay measurement circuitAbhishek Jain, Andrea Veggetti, Dennis Crippa, Pierluigi Rolandi. 1-6 [doi]
• A Software-Based Self-Test methodology for on-line testing of data TLBsGeorge Theodorou, S. Chatzopoulos, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos. 1 [doi]
• Characterization and handling of low-cost micro-architectural signatures in MPSoCsArmin Krieg, Johannes Grinschgl, Christian Steger, Reinhold Weiss, Andreas Genser, Holger Bock, Josef Haid. 1-6 [doi]
• Dependable embedded systems: The German research foundation DFG priority program SPP 1500Jörg Henkel, Oliver Bringmann, Andreas Herkersdorf, Wolfgang Rosenstiel, Norbert Wehn. 1 [doi]
• On-chip test comparison for protecting confidential data in secure ICsJean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. 1 [doi]
• Power-aware testing: The next stageXiaoqing Wen. 1 [doi]
• Memory reliability improvements based on maximized error-correcting codesValentin Gherman, Samuel Evain, Yannick Bonhomme. 1-6 [doi]
• Increasing autonomous fault-tolerant FPGA-based systems' lifetimeCristiana Bolchini, Antonio Miele, Chiara Sandionigi. 1-6 [doi]
• Test tool qualification through fault injectionQ. Wang, Andreas Wallin, Viacheslav Izosimov, Urban Ingelsson, Zebo Peng. 1 [doi]
• Adaptive multi-site testing for analog/mixed-signal circuits incorporating neighborhood informationEnder Yilmaz, Sule Ozev. 1-6 [doi]
• BIST design for analog cell matchingCandido Duarte, Henrique Cavadas, Pedro Coke, Luis Malheiro, Vitor Grade Tavares, Pedro Guedes de Oliveira. 1-6 [doi]
• VLSI Test technology: Why is the field not sexy enough?Said Hamdioui, Rob Aitken. 1 [doi]
• FP7 collaborative research project DIAMOND: Diagnosis, error modeling and correction for reliable systems designJaan Raik. 1 [doi]
• Online detection and recovery of transient errors in front-end structures of microprocessorsSyed Zafar Shazli, Mehdi Baradaran Tahoori. 1 [doi]
• Reducing wearout in embedded processors using proactive fine-grain dynamic runtime adaptationFabian Oboril, Mehdi Baradaran Tahoori. 1-6 [doi]
• Re-using chip level DFT at board levelXinli Gu, Jeff Rearick, Bill Eklow, Martin Keim, Jun Qian, Artur Jutman, Krishnendu Chakrabarty, Erik Larsson. 1 [doi]
• Through-Silicon-Via resistive-open defect analysisC. Metzler, Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel. 1 [doi]
• Multi-voltage aware resistive open fault modelingMohamed Tagelsir Mohammadat, Noohul Basheer Zain Ali, Fawnizu Azmadi Hussin. 1-6 [doi]
• Defect analysis in power mode control logic of low-power SRAMsLeonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine. 1 [doi]
• Coupling-based resistive-open defects in TAS-MRAM architecturesJ. Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, G. Prenat, Jérémy Alvarez-Herault, Ken Mackay. 1 [doi]
• Reducing test cost for mixed signal circuits "From TOETS to ELESIS"Mohamed Azimane. 1 [doi]
• Fast error detection through efficient use of hardwired resources in FPGAsGabriel L. Nazar, Luigi Carro. 1-6 [doi]
• Adaptive testing: Conquering process variationsEnder Yilmaz, Sule Ozev, Ozgur Sinanoglu, Peter Maxwell. 1-6 [doi]
• On-line software-based self-test of the Address Calculation Unit in RISC processorsPaolo Bernardi, Lyl M. Ciganda, Mauricio de Carvalho, Michelangelo Grosso, Jorge Luis Lagos-Benites, Ernesto Sánchez, Matteo Sonza Reorda, Oscar Ballan. 1-6 [doi]
• Indirect method for random jitter measurement on SoCs using critical path characterizationJae-Wook Lee, Ji Hwan (Paul) Chun, Jacob A. Abraham. 1-6 [doi]
• Introduction to the defect-oriented cell-aware test methodology for significant reduction of DPPM ratesFriedrich Hapke, Jürgen Schlöffel. 1-6 [doi]
• Enhanced wafer matching heuristics for 3-D ICsVasilis F. Pavlidis, Hu Xu, Giovanni De Micheli. 1 [doi]
• Combining dynamic slicing and mutation operators for ESL correctionUrmas Repinski, Hanno Hantson, Maksim Jenihhin, Jaan Raik, Raimund Ubar, Giuseppe Di Guglielmo, Graziano Pravadelli, Franco Fummi. 1-6 [doi]
• Testing of digitally assisted adaptive analog/RF systems using tuning knob - Performance space estimationAritra Banerjee, Shyam Kumar Devarakond, Shreyas Sen, Debashis Banerjee, Abhijit Chatterjee. 1 [doi]
• Funding project DIANA - Integrated diagnostics for the analysis of electronic failures in vehiclesPiet Engelke, Hermann Obermeir. 1 [doi]
• Efficient system-level aging predictionNadereh Hatami, Rafal Baranowski, Paolo Prinetto, Hans-Joachim Wunderlich. 1-6 [doi]
• On-chip temperature and voltage measurement for field testingYukiya Miura, Yasuo Sato, Yousuke Miyake, Seiji Kajihara. 1 [doi]
• Embedded synthetic instruments for Board-Level testingArtur Jutman, Sergei Devadze, Igor Aleksejev, Thomas Wenzel. 1 [doi]
• Bandwidth-aware test compression logic for SoC designsJakub Janicki, Jerzy Tyszer, Grzegorz Mrugalski, Janusz Rajski. 1-6 [doi]
• Impact of NBTI on analog componentsZhengliang Lv, Linda Milor, Shiyuan Yang. 1 [doi]
• On the detection of path delay faults by functional broadside testsIrith Pomeranz. 1-6 [doi]
• Built-in self-diagnosis exploiting strong diagnostic windows in mixed-mode testAlejandro Cook, Sybille Hellebrand, Hans-Joachim Wunderlich. 1-6 [doi]
• Time-division multiplexing for testing SoCs with DVS and multiple voltage islandsXrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji. 1-6 [doi]
• Multi-conditional SAT-ATPG for power-droop testingAlexander Czutro, Matthias Sauer, Ilia Polian, Bernd Becker. 1-6 [doi]
• A robust metric for screening outliers from analogue product manufacturing tests responsesShaji Krishnan, Hans G. Kerkhoff. 1-6 [doi]
• Introducing MEDIAN: A new COST Action on manufacturable and dependable multicore architectures at nanoscaleMarco Ottavi. 1 [doi]