Table of Contents

• Innovative practices session 4A variation-tolerant design of circuits/systemsArijit Raychowdhury. 1 [doi]
• HLDTL: High-performance, low-cost, and double node upset tolerant latch designAibin Yan, Zhengfeng Huang, Maoxiang Yi, Jie Cui, Huaguo Liang. 1-6 [doi]
• Flip-flop clustering based trace signal selection for post-silicon debugYun Cheng, Huawei Li, Ying Wang, Yingke Gao, Bo Liu, Xiaowei Li 0001. 1-6 [doi]
• A novel design-for-security (DFS) architecture to prevent unauthorized IC overproductionUjjwal Guin, Ziqi Zhou, Adit Singh. 1-6 [doi]
• Knob non-idealities in learning-based post-production tuning of analog/RF ICs: Impact & remediesYichuan Lu, Georgios Volanis, Kiruba S. Subramani, Angelos Antonopoulos, Yiorgos Makris. 1-6 [doi]
• Innovative practices session 10C formal verification practices in industryHuawei Li, Xiaowei Li. 1 [doi]
• Innovative practices session 2C: "How is industry simplifying analog test"Rubin A. Parekhji, Srinivas Modekurty. 1 [doi]
• Accurate jitter decomposition in high-speed linksYan Duan, Degang Chen. 1-6 [doi]
• Test-set reordering for improving diagnosabilityCheng Xue, R. D. (Shawn) Blanton. 1-6 [doi]
• Special session on early life failuresJyotirmoy Deshmukh, Wolfgang Kunz, Hans-Joachim Wunderlich, Sybille Hellebrand. 1 [doi]
• Fast WAT test structure for measuring Vt variance based on latch-based comparatorsKao-Chi Lee, Kai-Chiang Wu, Chih-Ying Tsai, Mango Chia-Tso Chao. 1-6 [doi]
• Leveraging Systematic Unidirectional Error-Detecting Codes for fast STT-MRAM cacheNour Sayed, Fabian Oboril, Rajendra Bishnoi, Mehdi Baradaran Tahoori. 1-6 [doi]
• Innovative practices session 7C automotive quality assurancePeter Sarson. 1 [doi]
• Methodology of generating dual-cell-aware testsYu-Hao Huang, Ching-Ho Lu, Tse-Wei Wu, Yu-Teng Nien, Ying-Yen Chen, Max Wu, Jih-Nung Lee, Mango C.-T. Chao. 1-6 [doi]
• ForewordYiorgos Makris, Srivaths Ravi, Amit Majumdar. 1-2 [doi]
• Efficient SAT-based generation of hazard-activated TSOF testsJan Burchard, Dominik Erb, Sudhakar M. Reddy, Adit D. Singh, Bernd Becker 0001. 1-6 [doi]
• Innovative practices session 9C DFT and data for diagnosticsKun Young Chung, Stefano Di Carlo. 1 [doi]
• Structured scan patterns retargeting for dynamic instruments accessAhmed Ibrahim, Hans G. Kerkhoff. 1-6 [doi]
• An optimised SDD ATPG and SDQL computation method across different pattern setsWilson Pradeep, Prakash Narayanan, Rubin A. Parekhji. 1-6 [doi]
• A methodology for estimating memory lifetime using a system-level accelerated life test and error-correcting codesDae-Hyun Kim, Linda Milor. 1-6 [doi]
• Innovative practices session 5C automotive test solutionsPete Sarson, Stefano Di Carlo. 1 [doi]
• Innovative practices session 3C hardware securityJ. V. Rajendran, Peilin Song, Suriya Natarajan. 1 [doi]
• Innovative practices session 4C data analytics in testSuriya Natarajan, Abhijit Sathaye. 1 [doi]
• Asymmetric sizing: An effective design approach for SRAM cells against BTI agingXuan Zuo, Sandeep K. Gupta. 1-6 [doi]
• Learning the process for correlation analysisSebastian Siatkowski, Li-C. Wang, Nik Sumikawa, LeRoy Winemberg. 1-6 [doi]
• A technique for dynamic range improvement of intermodulation distortion products for an Interpolating DAC-based Arbitrary Waveform Generator using a phase switching algorithmPeter Sarson, Shohei Shibuya, Tomonori Yanagida, Haruo Kobayashi. 1-6 [doi]
• Fail data reduction for diagnosis of scan chain faults under transparent-scanIrith Pomeranz. 1-6 [doi]
• Innovative practices session 10B innovative practices in Asia-2: From cost perspectiveKazumi Hatayama, Masahiro Ishida. 1 [doi]
• Innovative practices session 6C DFT for functional safetyPrashant Goteti, Sreejit Chakravarty. 1 [doi]
• Keynote address: Opening keynoteAhmad Bahai. 1 [doi]
• A low-cost method for separation and accurate estimation of ADC noise, aperture jitter, and clock jitterShravan K. Chaganti, Li Xu, Degang Chen. 1-6 [doi]
• Adaptive test flow for mixed-signal ICsHaralampos-G. D. Stratigopoulos, Christian Streitwieser. 1-6 [doi]
• Comprehensive investigation of gate oxide short in FinFETsRoya Dibaj, Dhamin Al-Khalili, Maitham Shams. 1-6 [doi]
• A framework for fast test generation at the RTLKelson Gent, Akash Agrawal, Michael S. Hsiao. 1-6 [doi]
• Innovative practices session 9B innovative practices in Asia-1: From quality perspectiveKazumi Hatayama, Masahiro Ishida. 1 [doi]
• An analytical model for predicting the residual life of an IC and design of residual-life meterMd. Nazmul Islam, Sandip Kundu. 1-6 [doi]
• Performance-aware reliability assessment of heterogeneous chipsAthanasios Chatzidimitriou, Manolis Kaliorakis, Sotiris Tselonis, Dimitris Gizopoulos. 1-6 [doi]
• Test-cost optimization in a scan-compression architecture using support-vector regressionZipeng Li, Jonathon E. Colburn, Vinod Pagalone, Kaushik Narayanun, Krishnendu Chakrabarty. 1-6 [doi]
• A new delay testing signal scheme robust to power distribution network impedance variationClaude Thibeault, Ali Louati. 1-6 [doi]
• Fiscal: Firmware identification using side-channel power analysisDeepak Krishnankutty, Ryan Robucci, Nilanjan Banerjee, Chintan Patel. 1-6 [doi]
• Using piecewise-functional broadside tests for functional broadside test compactionIrith Pomeranz. 1-6 [doi]
• Innovative practices session 1C screening for layout sensitive defectsArani Sinha, Nitin Chaudhary. 1 [doi]
• Innovative practices session 11C SoC testingYu Huang. 1 [doi]
• At-speed capture global noise reduction & low-power memory test architectureBonita Bhaskaran, Sailendra Chadalavada, Shantanu Sarangi, Nithin Valentine, Venkat Abilash Reddy Nerallapally, Ayub Abdollahian. 1-6 [doi]
• Analysis of an efficient on-chip servo-loop technique for reduced-code static linearity test of pipeline ADCsGuillaume Renaud, Marc Margalef-Rovira, Manuel J. Barragan, Salvador Mir. 1-6 [doi]
• Dynamically obfuscated scan for protecting IPs against scan-based attacks throughout supply chainDongrong Zhang, Miao Tony He, Xiaoxiao Wang, Mark Tehranipoor. 1-6 [doi]
• Aging monitor reuse for small delay fault testingChang Liu, Michael A. Kochte, Hans-Joachim Wunderlich. 1-6 [doi]
• Keynote address tribute to Professor Mel Breuer: Contributions to CAD and TestSandeep Gupta, Miron Abramovici, Magdy Abadir, Sridhar Narayanan. 1 [doi]
• On-line diagnosis and compensation for parametric failures in linear state variable circuits and systems using time-domain checksum observersMd Imran Momtaz, Suvadeep Banerjee, Abhijit Chatterjee. 1-6 [doi]