Aibin Yan, Zhengfeng Huang, Maoxiang Yi, Jie Cui, Huaguo Liang. HLDTL: High-performance, low-cost, and double node upset tolerant latch design. In 35th IEEE VLSI Test Symposium, VTS 2017, Las Vegas, NV, USA, April 9-12, 2017. pages 1-6, IEEE, 2017. [doi]
Abstract is missing.