Table of Contents

• Structural Software-Based Self-Test of Network-on-ChipAtefe Dalirsani, Michael E. Imhof, Hans-Joachim Wunderlich. 1-6 [doi]
• New topic session 7B: Challenges and opportunities in test and design for test (DFT) of MEMS sensorsBozena Kaminska, Bernard Courtois, Bozena Kaminska, Mary Ann Maher. 1 [doi]
• Development and empirical verification of an accuracy model for the power down leakage testsJae-woong Jeong, Sule Ozev, Friedrich Taenzler, Hui-Chuan Chao. 1-6 [doi]
• Test-time optimization in NOC-based manycore SOCs using multicast routingMukesh Agrawal, Krishnendu Chakrabarty. 1-6 [doi]
• Hot topic session 12B: Stay relevant with standards-based DFTC. J. Clark, Víctor H. Champac. 1 [doi]
• Hot topic session 12A: Split manufacturing - IARPA's TIC programDean Collins, Ramesh Karri, Dean Collins. 1-2 [doi]
• Fast evaluation of test vector sets using a simulation-based statistical metricShahrzad Mirkhani, Jacob A. Abraham. 1-6 [doi]
• Functional block extraction for hardware security detection using time-integrated and time-resolved emission measurementsFranco Stellari, Peilin Song, Herschel A. Ainspan. 1-6 [doi]
• Innovative practices session 3C: Solving today's test challengesJohn Kim, Wolfgang Meyer, T. M. Mak, Amitava Majumdar. 1 [doi]
• Special session 8B - Panel: In-field testing of SoC devices: Which solutions by which players?Jacob A. Abraham, Xinli Gu, Teresa MacLaurin, Janusz Rajski, Paul G. Ryan, Dimitris Gizopoulos, Matteo Sonza Reorda. 1-2 [doi]
• Active defense against counterfeiting attacks through robust antifuse-based on-chip locksAbhishek Basak, Yu Zheng, Swarup Bhunia. 1-6 [doi]
• Fault modeling and test algorithm creation strategy for FinFET-based memoriesGurgen Harutyunyan, G. Tshagharyan, Valery A. Vardanian, Yervant Zorian. 1-6 [doi]
• A method for phase noise extraction from data communicationAllan Ecker, Mani Soma. 1-6 [doi]
• Special session 4A: Elevator talksJennifer Dworak. 1 [doi]
• Fault tolerant nanoarray circuits: Automatic design and verificationP. Ranone, G. Turvani, F. Riente, M. Graziano, Massimo Ruo Roch, Maurizio Zamboni. 1-6 [doi]
• Innovative practices session 2C: Advanced in yield learningYen-Tzu Lin, Brady Benware, Brian Stine, Azeez Bhavnagarwala. 1 [doi]
• Identification of testable representative paths for low-cost verification of circuit performance during manufacturing and in-field testsJifeng Chen, LeRoy Winemberg, Mohammad Tehranipoor. 1-6 [doi]
• Special session 11B: ITRS adaptive test updateJohn Carulli. 1 [doi]
• An efficient diagnosis method to deal with multiple fault-pairs simultaneously using a single circuit modelCheng-Hung Wu, Kuen-Jong Lee, Wei-Cheng Lien. 1-6 [doi]
• Innovative practices session 5C: Machine learning and data analysis in testSounil Biswas, John Carulli, Dragoljub Gagi Drmanac, Arpan Bhattacherjee. 1 [doi]
• Built-in self-test for manufacturing TSV defects before bondingGiorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Hakim Zimouche. 1-6 [doi]
• New topic session 2B: Co-design and reliability of power electronic modules - Current status and future challengesBozena Kaminska, Bernard Courtois, Chris Bailey. 1 [doi]
• Built-in self test methodology for diagnosis of backend wearout mechanisms in SRAM cellsWoongrae Kim, Linda Milor. 1-6 [doi]
• On the use of multi-cycle tests for storage of two-cycle broadside testsIrith Pomeranz. 1-6 [doi]
• Continuous wave radar circuitry testing using OFDM techniqueMohamed Metwally, Nicholai L'Esperance, Tian Xia, Mustapha Slamani. 1-6 [doi]
• Test generation and design-for-testability for flow-based mVLSI microfluidic biochipsKai Hu, Tsung-Yi Ho, Krishnendu Chakrabarty. 1-6 [doi]
• Alternative "safe" test of hysteretic power convertersXian Wang, Blanchard Kenfack, Estella Silva, Abhijit Chatterjee. 1-6 [doi]
• Accurate and efficient method of jitter and noise separation and its application to ADC testingLi Xu, Degang Chen. 1-5 [doi]
• Hot topic session 9C: Test and fault tolerance for emerging memory technologiesSuriya Natarajan, Amitava Majumdar, Jeyavijayan Rajendran. 1 [doi]
• Improving CMOS open defect coverage using hazard activated testsChao Han, Adit D. Singh. 1-6 [doi]
• Special session 11C: Young professionals in test - Elevator talksAlodeep Sanyal, Yanjing Li, Alodeep Sanyal. 1 [doi]
• Fault simulation with test switching for static test compactionIrith Pomeranz. 1-6 [doi]
• A built-in self-test technique for load inductance and lossless current sensing of DC-DC convertersTao Liu, Chao Fu, Sule Ozev, Bertan Bakkaloglu. 1-6 [doi]
• A built-in gain calibration technique for RF low-noise amplifiersYa-Ru Wu, Yi-Keng Hsieh, Po-Chih Ku, Liang-Hung Lu. 1-6 [doi]
• Innovative practices session 4C: Disruptive solutions in the non-digital worldAmitava Majumdar, Suriya Natarajan, Amitava Majumdar, Stephen K. Sunter, Prashant Goteti, Ke Huang. 1 [doi]
• Reliability enhancement using in-field monitoring and recovery for RF circuitsDoohwang Chang, Sule Ozev, Bertan Bakkaloglu, Sayfe Kiaei, Engin Afacan, Günhan Dündar. 1-6 [doi]
• Detection, diagnosis, and repair of faults in memristor-based memoriesSachhidh Kannan, Naghmeh Karimi, Ramesh Karri, Ozgur Sinanoglu. 1-6 [doi]
• Special session 8A: E.J. McCluskey Doctoral Thesis Award semi-finalMichele Portolan, Michail Maniatakos. 1 [doi]
• Testing methods for a write-assist disturbance-free dual-port SRAMHao-Yu Yang, Chen-Wei Lin, Chao-Ying Huang, Ching-Ho Lu, Chen-An Lai, Mango Chia-Tso Chao, Rei-Fu Huang. 1-6 [doi]
• Improved power supply noise control for pseudo functional testTengteng Zhang, Duncan M. Hank Walker. 1-6 [doi]
• Special session 12C: Young professionals in test - Town meetingAlodeep Sanyal, Yanjing Li, Yervant Zorian. 1 [doi]
• Innovative practices session 1C: Existing/emerging low power techniquesCharutosh Dixit, Ramesh C. Tekumalla, Wei Zhao, Nilanjan Mukherjee, Vivek Chickermane. 1 [doi]
• Innovative practices session 7C: Reduced pin-count testing - How low can we go?Stephen K. Sunter, Steve Comen, Paul Berndt, Ram Rajamani. 1 [doi]
• TSV aware timing analysis and diagnosis in paths with multiple TSVsCarolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel. 1-6 [doi]
• Auto-identification of positive feedback loops in multi-state vulnerable circuitsZhiqiang Liu, You Li, Randall L. Geiger, Degang Chen. 1-5 [doi]
• At-speed interconnect testing and test-path optimization for 2.5D ICsRan Wang, Krishnendu Chakrabarty, Sudipta Bhawmik. 1-6 [doi]
• Extraction of threshold voltage degradation modeling due to Negative Bias Temperature Instability in circuits with I/O measurementsSoonyoung Cha, Chang-Chih Chen, Taizhi Liu, Linda S. Milor. 1-6 [doi]
• SMV methodology enhancements for high speed I/O links of SoCsAndres Viveros-Wacher, Ricardo Alejos, Liliana Alvarez, Israel Diaz-Castro, Brenda Marcial, Gaston Motola-Acuna, Edgar-Andrei Vega-Ochoa. 1-5 [doi]
• Quality versus cost analysis for 3D Stacked ICsMottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen. 1-6 [doi]
• Special session 8C: Hot topic: Designers' and test researchers' roles in analog design-for-testMasahiro Ishida, Takahiro J. Yamaguchi, Mani Soma, Terri Fiez, Mike Peng Li. 1 [doi]
• Innovative practices session 10C: Advances in DFT and compressionRohit Kapur, Irith Pomeranz. 1 [doi]
• On-chip voltage-droop prediction using support-vector machinesFangming Ye, Farshad Firouzi, Yang Yang, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori. 1-6 [doi]
• Multi-channel testing architecture for high-speed eye-diagram using pin electronics and subsampling monobit reconstruction algorithmsThomas Moon, Hyun Woo Choi, David C. Keezer, Abhijit Chatterjee. 1-6 [doi]
• Atomic model learning: A machine learning paradigm for post silicon debug of RF/analog circuitsSabyasachi Deyati, Barry John Muldrey, Aritra Banerjee, Abhijit Chatterjee. 1-6 [doi]
• A 4-GHz universal high-frequency on-chip testing platform for IP validationPing-Lin Yang, Cheng-Chung Lin, Ming-Zhang Kuo, Sang-Hoo Dhong, Chien-Min Lin, Kevin Huang, Ching-Nen Peng, Min-Jer Wang. 1-6 [doi]
• A shared memory based parallel diagnosis systemX. Cai, Emil Gizdarski, D. Landau. 1-6 [doi]
• Accelerated online error detection in many-core microprocessor architecturesManolis Kaliorakis, Mihalis Psarakis, Nikos Foutris, Dimitris Gizopoulos. 1-6 [doi]
• Accelerating capture of infrequent errors on ATE for silicon TV tunersY. Fan, A. Verma, D. S. Trager, R. K. Poorfard, J. Janney, S. Kumar. 1-6 [doi]
• Power/ground supply voltage variation-aware delay test pattern generationLu Wang, Xutao Wang, Milad Maleki, Bao Liu. 1-6 [doi]
• Test planning and test access mechanism design for stacked chips using ILPBreeta SenGupta, Erik Larsson. 1-6 [doi]
• Efficient Monte Carlo-based analog parametric fault modellingHaralampos-G. D. Stratigopoulos, Stephen Sunter. 1-6 [doi]
• Unstructured text: Test analysis techniques applied to non-test problemsAnne Gattiker. 1-4 [doi]
• Modeling location based wafer die yield variation in estimating 3D stacked IC yield from wafer to wafer stackingEshan Singh. 1-6 [doi]
• Special session 4B: Panel: Testing and calibration for power management circuitsSule Ozev, Bertan Bakkaloglu, Sule Ozev. 1 [doi]
• Self-heating thermal-aware testing of FPGAsAbdulazim Amouri, Jochen Hepp, Mehdi Baradaran Tahoori. 1-6 [doi]
• Phase-locked loop design with SPO detection and charge pump trimming for reference spur suppressionSen-Wen Hsiao, Chung-Chun Chen, Randy Caplan, Jeff Galloway, Blake Gray, Abhijit Chatterjee. 1-6 [doi]