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Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik. At-speed interconnect testing and test-path optimization for 2.5D ICs. In IEEE 32nd VLSI Test Symposium, VTS 2014, Napa, CA, USA, April 13-17, 2014. pages 1-6, IEEE, 2014. [doi]
Abstract is missing.