Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik. At-speed interconnect testing and test-path optimization for 2.5D ICs. In IEEE 32nd VLSI Test Symposium, VTS 2014, Napa, CA, USA, April 13-17, 2014. pages 1-6, IEEE, 2014. [doi]
@inproceedings{WangCB14,
title = {At-speed interconnect testing and test-path optimization for 2.5D ICs},
author = {Ran Wang and Krishnendu Chakrabarty and Sudipta Bhawmik},
year = {2014},
doi = {10.1109/VTS.2014.6818770},
url = {http://dx.doi.org/10.1109/VTS.2014.6818770},
researchr = {https://researchr.org/publication/WangCB14},
cites = {0},
citedby = {0},
pages = {1-6},
booktitle = {IEEE 32nd VLSI Test Symposium, VTS 2014, Napa, CA, USA, April 13-17, 2014},
publisher = {IEEE},
}