Wolfgang Meyer - researchr alias

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Viewing Publication 1 - 24 from 24

2017

Hochschule 2027Raphael Zender, Ulrike Lucke, Markus Von Der Heyde, Wolfgang Meyer. gi 2017: 1687-1688 [doi]

2016

Hochschule 2026Ulrike Lucke, Markus Von Der Heyde, Wolfgang Meyer. gi 2016: 899 [doi]

2014

Innovative practices session 3C: Solving today's test challengesJohn Kim, Wolfgang Meyer, T. M. Mak, Amitava Majumdar. vts 2014: 1 [doi]

2008

Load balancing algorithms based on gradient methods and their analysis through algebraic graph theoryAndrey G. Bronevich, Wolfgang Meyer. jpdc, 68(2):209-220, 2008. [doi]

2007

Classification of Highly Unbalanced CYP450 Data of Drugs Using Cost Sensitive Machine Learning TechniquesTatjana Eitrich, Achim Kless, Claudia Druska, Wolfgang Meyer, Johannes Grotendorst. jcisd, 47(1):92-103, 2007. [doi]

Robotic Cycle Shop Control based on deterministic Correlation MapsWolfgang Meyer, Claudia Fiedler. icra 2007: 1280-1285 [doi]

Dynamic Load Balancing of Cycle Shops Based on Correlation FunctionsWolfgang Meyer, Claudia Fiedler. imecs 2007: 1522-1527

2006

Auto Correlation and Collision Avoidance in Robotic Flow ShopsWolfgang Meyer, Claudia Fiedler. cdc 2006: 1037-1042 [doi]

Trends in Test: Challenges and TechniquesWolfgang Meyer. hldvt 2006: 37 [doi]

Mission control by coordinating shared resourcesWolfgang Meyer, Claudia Fiedler. sysose 2006: 1-13 [doi]

2005

Designing transitory routing controllers for hybrid plantsClaudia Fiedler, Wolfgang Meyer, Arne von Drathen. IEEEcca 2005: 934-939 [doi]

1998

Partitioning and Optimizing Controllers Synthesized from Hierarchical High-Level DescriptionsAndrew Seawright, Wolfgang Meyer. dac 1998: 770-775 [doi]

1997

Design and Synthesis of Array Structured Telecommunication Processing ApplicationsWolfgang Meyer, Andrew Seawright, Fumiya Tada. dac 1997: 486-491 [doi]

1996

A system for compiling and debugging structured data processing controllersAndrew Seawright, Joseph Buck, Ulrich Holtmann, Wolfgang Meyer, Barry M. Pangrle, Rob Verbrugghe. eurodac 1996: 86-91 [doi]

1995

Active timing multilevel fault-simulation with switch-level accuracyWolfgang Meyer, Raul Camposano. tcad, 14(10):1241-1256, 1995. [doi]

1994

Hierarchische Mehr-Ebenen-Fehlersimulation mit Modellen der Schalter-EbeneWolfgang Meyer. PhD thesis, Universität Paderborn, 1994.

1993

Fast Hierarchical Multi-Level Fault Simulation of Sequential Circuits with Switch-Level AccuracyWolfgang Meyer, Raul Camposano. dac 1993: 515-519 [doi]

CMOS Bridges and Resistive Transistor Faults: I::DDQ:: versus Delay EffectsHeinrich Theodor Vierhaus, Wolfgang Meyer, Uwe Gläser. itc 1993: 83-91

Fault behavior and testability of asynchronous CMOS circuitsHeinrich Theodor Vierhaus, Wolfgang Meyer, Uwe GlÃ¤ser, Raul Camposano. jsa, 38(1-5):223-228, 1993. [doi]

1992

CMOS transistor faults and bridging faults: Testability by delay effects and overcurrentsUwe Hübner, Wolfgang Meyer, Heinrich Theodor Vierhaus. jsa, 35(1-5):377-382, 1992. [doi]

Geometrische Methoden zur Lösung von Job-Shop Problemen und deren VerallgemeinerungenWolfgang Meyer. PhD thesis, University of Osnabrück, Germany, 1992. [doi]

1988

Scheduling two irregular polygonsPeter Brucker, Wolfgang Meyer. DAM, 20(2):91-100, 1988. [doi]

1987

Approximation of a set of points by points of a gridPeter Brucker, Wolfgang Meyer. computing, 38(4):341-345, 1987. [doi]

1978

New Materials for Superconductive Communication CablesWolfgang Meyer. tcom, 26(4):449-458, 1978. [doi]

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