Abstract is missing.
- A hierarchical approach to analog behavioral modeling of neural networks using HDL-AM. Ahmed, H. F. Ragaie, H. Haddara. 2-9 [doi]
- BRASIL: the Braunschweig mixed-mode-simulator for integrated circuitsUlrich Bretthauer, Ernst-Helmut Horneber. 10-14 [doi]
- Generalized coupling as a way to improve the convergence in relaxation-based solversVladimir B. Dmitriev-Zdorov. 15-20 [doi]
- Power analysis for sequential circuits at logic levelMatthias A. Senn, Peter H. Schneider, Bernd Wurth. 22-27 [doi]
- State assignment for FSM low power designManfred Koegst, Klaus Feske, Günter Franke. 28-33 [doi]
- Specification and design of electronic control unitsJürgen Bortolazzi, Thomas Hirth, Thomas Raith. 36-41 [doi]
- Exploration of hardware/software design space through a codesign of robot arm controllerMohamed Abid, Adel Changuel, Ahmed Amine Jerraya. 42-47 [doi]
- Design of an adaptive motors controller based on fuzzy logic using behavioral synthesisAdel Changuel, Ahmed Amine Jerraya, Robin Rolland. 48-52 [doi]
- Implementing fuzzy control systems using VHDL and statechartsValentina Salapura, Volker Hamann. 53-58 [doi]
- A top down mixed-signal design methodology using a mixed-signal simulator and analog HDLT. Murayama, Y. Gendai. 59-64 [doi]
- New approach in gate-level glitch modellingDirk Rabe, Wolfgang Nebel. 66-71 [doi]
- A new concept for accurate modeling of VLSI interconnections and its application for timing simulationBernhard Wunder, Gunther Lehmann, Klaus D. Müller-Glaser. 72-77 [doi]
- Timing verification for asynchronous designRhodri M. Davies, John V. Woods. 78-83 [doi]
- A system for compiling and debugging structured data processing controllersAndrew Seawright, Joseph Buck, Ulrich Holtmann, Wolfgang Meyer, Barry M. Pangrle, Rob Verbrugghe. 86-91 [doi]
- A graphical data management system for HDL-based ASIC design projectsClaus Mayer, Jörg Pleickhardt, Hans Sahm. 92-97 [doi]
- An integrated concept for design project planning and design flow controlMichael Ryba, Utz G. Baitinger. 98-103 [doi]
- Automatic workflow generationVladimir A. Shepelev, Stephen W. Director. 104-109 [doi]
- Synthesis from mixed specificationsGiovanni De Micheli, Vincnet J. Mooney III, Claudionor Nunes Coelho, Toshiyuki Sakamoto. 114-119 [doi]
- A system level HW/SW partitioning and optimization toolMarkus Schwiegershausen, Holger Kropp, Peter Pirsch. 120-125 [doi]
- A new HW/SW partitioning algorithm for synthesizing the highest performance pipelined ASIPs with multiple identical FUsMasaharu Imai, Nguyen-Ngoc Bình, Akichika Shiomi. 126-131 [doi]
- Automatic structuring and optimization of hierarchical designsHeinz-Josef Eikerling, Wolfgang Rosenstiel. 134-139 [doi]
- Controller optimization for protocol intensive applicationsAndrew Crews, Forrest Brewer. 140-145 [doi]
- Library based technology mapping using multiple domain representationsJ. Bullmann, Wolfgang Rosenstiel, E. Schubert, Udo Kebschull. 146-150 [doi]
- Compilation of optimized OBDD-algorithmsStefan Höreth. 152-157 [doi]
- Incremental re-encoding for symbolic traversal of product machinesGianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Stefano Quer, Robert K. Brayton, Ellen Sentovich. 158-163 [doi]
- MORE: an alternative implementation of BDD packages by multi-operand synthesisAndreas Hett, Bernd Becker, Rolf Drechsler. 164-169 [doi]
- Decomposed symbolic forward traversals of large finite state machinesStefano Quer, Gianpiero Cabodi, Paolo Camurati. 170-175 [doi]
- COMET: a hardware-software codesign methodologyMichael J. Knieser, Christos A. Papachristou. 178-183 [doi]
- Mapping statechart models onto an FPGA-based ASIP architectureChristian Veith, Klaus Buchenrieder, Andreas Pyttel. 184-189 [doi]
- MILP based task mapping for heterogeneous multiprocessor systemsArmin Bender. 190-197 [doi]
- Instruction selection for embedded DSPs with complex instructionsRainer Leupers, Peter Marwedel. 200-205 [doi]
- Rapid performance estimation for system designSanjiv Narayan, Daniel D. Gajski. 206-211 [doi]
- Hierarchical behavioral partitioning for multicomponent synthesisVinoo Srinivasan, Nand Kumar, Ranga Vemuri. 212-217 [doi]
- Testable path delay fault cover for sequential circuitsAngela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar. 220-226 [doi]
- Efficient random testing with global weightsArno Kunzmann. 227-232 [doi]
- Fault tolerant and BIST design of a FIFO cellPaolo Prinetto, Fulvio Corno, Matteo Sonza Reorda. 233-238 [doi]
- A digital method for testing embedded switched capacitor filtersM. Robson, G. Russell. 239-244 [doi]
- Hardware/software-cosimulation for mechatronic system designGeorg Pelz, Jürgen Bielefeld, Günther Hess, Günter Zimmer. 246-251 [doi]
- CoWare - a design environment for heterogenous hardware/software systemsKarl van Rompaey, Ivo Bolsens, Hugo De Man, Diederik Verkest. 252-257 [doi]
- An approach for integrated specification and design of real-time systemsYankin Tanurhan, H. Gölz, Stefan Schmerler, Klaus D. Müller-Glaser. 258-263 [doi]
- An integrated approach to engineering computer systemsD. Gareth Evans, Peter N. Green, Derrick Morris. 264-269 [doi]
- Spotlights on recent developments in microsystem technologyStephanus Büttgenbach. 274-279 [doi]
- CAD of microsystems - a challenge for system engineeringKlaus D. Müller-Glaser. 280-281 [doi]
- A heuristic covering technique for optimizing average-case delay in the technology mapping of asynchronous burst-mode circuitsPeter A. Beerel, Wei-Chun Chou, Kenneth Y. Yun. 284-289 [doi]
- Automatic synthesis of extended burst-mode circuits using generalized C-elementsKenneth Y. Yun. 290-295 [doi]
- Storage optimization by replacing some flip-flops with latchesYoun-Long Lin, Tsung-Yi Wu. 296-301 [doi]
- Assignment of storage values to sequential read-write memoriesSabih H. Gerez, Erwin G. Woutersen. 302-307 [doi]
- Estimation of the number of routing layers and total wirelength in a PCB through wiring distribution analysisIvan Hom, John J. Granacki. 310-315 [doi]
- Describing space-continuous models of microelectromechanical devices for behavioral simulationZeljko Mrcarica, Helmut Detter, D. Glozic, Vanco B. Litovski. 316-321 [doi]
- Simulation and design optimization of microsystems based on standard simulators and adaptive search techniquesWolfgang Süß, Horst Eggert, M. Georges-Schleuter, Wilfried Jakob, S. Meinzer, Alexander Quinte. 322-327 [doi]
- Clock optimization for high-performance pipelined designHsiao-Ping Juan, Smita Bakshi, Daniel D. Gajski. 330-335 [doi]
- False path exclusion in delay analysis of RTL-based datapath-controller designsChristos A. Papachristou, Mehrdad Nourani. 336-341 [doi]
- Timing optimization by an improved redundancy addition and removal techniqueLuis Entrena, Emilio Olías, Javier Uceda, José Alberto Espejo. 342-347 [doi]
- Physical design CAD in deep sub-micron eraTakashi Mitsuhashi, Masami Murakata, Kenji Yoshida, T. Aoki. 350-355 [doi]
- EXPLORER: an interactive floorplanner for design space explorationHenrik Esbensen, Ernest S. Kuh. 356-361 [doi]
- A practical clock router that accounts for the capacitance derived from parallel and cross segmentsMitsuho Seki, Kazuo Kato, S. Kobayashi, Kouki Tsurusaki. 362-367 [doi]
- Component selection in resource shared and pipelined DSP applicationsSmita Bakshi, Daniel D. Gajski, Hsiao-Ping Juan. 370-375 [doi]
- Module assignment for low powerMassoud Pedram, Jui-Ming Chang. 376-381 [doi]
- A high-level synthesis approach to optimum design of self-checking circuitsMariagiovanna Sami, Anna Antola, Vincenzo Piuri. 382-387 [doi]
- Global stacking for analog circuitsBogdan G. Arsintescu, Sorin A. Spânoche. 392-397 [doi]
- TINA: analog placement using enumerative techniques capable of optimizing both area and net lengthTobias H. Abthoff, Frank M. Johannes. 398-403 [doi]
- Software methodologies for VHDL code static analysis based on flow graphsDonatella Sciuto, Luciano Baresi, Cristiana Bolchini. 406-411 [doi]
- A VHDL reuse workbenchGunther Lehmann, Klaus D. Müller-Glaser, Bernhard Wunder. 412-417 [doi]
- Beyond VHDL: textual formalisms, visual techniques, or both?Franz J. Rammig. 420-427 [doi]
- Object-oriented hardware modelling - where to apply and what are the objects?Guido Schumacher, Wolfgang Nebel. 428-433 [doi]
- Hardware/software partitioning of VHDL system specificationsPetru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli. 434-439 [doi]
- BDD-based testability estimation of VHDL designsEnrico Macii, Massimo Poncino, Fabrizio Ferrandi, Franco Fummi, Donatella Sciuto. 444-449 [doi]
- VHDL fault simulation for defect-oriented test and diagnosis of digital ICsJoão Paulo Teixeira, F. Celeiro, L. Dias, J. Ferreira, Marcelino B. Santos. 450-455 [doi]
- Model generation of test logic for macrocell based designsEduardo de la Torre, J. Calvo, Javier Uceda. 456-461 [doi]
- A fault model for VHDL descriptions at the register transfer levelTeresa Riesgo, Javier Uceda. 462-467 [doi]
- The maximal VHDL subset with a cycle-level abstractionWendell C. Baker, A. Richard Newton. 470-475 [doi]
- Automatic diagnosis may replace simulation for correcting simple design errorsAyman M. Wahba, Dominique Borrione. 476-481 [doi]
- A refinement calculus for VHDLPeter T. Breuer, Carlos Delgado Kloos, Natividad Martínez Madrid, Luis Sánchez, Andrés Marín. 482-487 [doi]
- Analysis of different protocol description styles in VHDL for high-level synthesisMaher Rahmouni, Ahmed Amine Jerraya, Polen Kission, Antônio C. Mesquita, Aloysio Pedroza, Luci Pirmez. 490-495 [doi]
- Hardware synthesis from requirement specificationsKonrad Feyerabend, Rainer Schlör. 496-501 [doi]
- Modeling ASIC memories in VHDLEkambaram Balaji, Prabhu Krishnamurthy. 502-508 [doi]
- Stepwise refinement of behavioral VHDL specifications by separation of synchronization and functionalityClaus Schneider, Wolfgang Ecker. 509-514 [doi]
- Synchronous parallel controller synthesis from behavioural multiple-process VHDL descriptionKrzysztof Bilinski, Erik L. Dagless, Jaroslaw Mirkowski. 516-521 [doi]
- Specification and management of timing constraints in behavioral VHDLFrancesco Curatelli, Marco Chirico, Leonardo Mangeruca. 522-527 [doi]
- Towards maximising the use of structural VHDL for synthesisKevin O'Brien, Serge Maginot, Anne Robert. 528-533 [doi]
- Fault behavior observation of a microprocessor system through a VHDL simulation-based fault injection experimentPaolo Prinetto, Alfredo Benso, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Arturo M. Amendola, Leonardo Impagliazzo, P. Marmo. 536-541 [doi]
- System design using an integrated specification and performance modeling methodologyAmbar Sarkar. 542-547 [doi]
- An extendable MIPS-I processor kernel in VHDL for hardware/software co-designMichael Gschwind, Dietmar Maurer. 548-553 [doi]
- VHDL 1076.1 - analog and mixed signal extensions to VHDLErnst Christen, Kenneth Bakalar. 556-561 [doi]
- Entity overloading for mixed-signal abstraction in VHDLC.-J. Richard Shi. 562-567 [doi]
- KIR - a graph-based model for description of mixed analog/digital systemsChristoph Grimm 0001, Klaus Waldschmidt. 568-573 [doi]