Markus Schwiegershausen - researchr alias

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Viewing Publication 1 - 10 from 10

1997

Implementation of pipelined multipliers on Xilinx FPGAsTien-Toan Do, Holger Kropp, Markus Schwiegershausen, Peter Pirsch. fpl 1997: 51-60

Heterogeneous Multiprocessor Scheduling and Allocation using Evolutionary AlgorithmsCarsten Reuter, Markus Schwiegershausen, Peter Pirsch. asap 1997: 294-303 [doi]

Ein Verfahren zur Optimierung heterogener Multiprozessorsysteme mittels linearer ProgrammierungMarkus Schwiegershausen. PhD thesis, University of Hanover, 1997. [doi]

1996

A CAD tool for the optimization of video signal processor architecturesHolger Kropp, Markus Schwiegershausen, Peter Pirsch. icassp 1996: 1244-1247 [doi]

A system level HW/SW partitioning and optimization toolMarkus Schwiegershausen, Holger Kropp, Peter Pirsch. eurodac 1996: 120-125 [doi]

1995

A formal approach for the optimization of heterogeneous multiprocessors for complex image processing schemesMarkus Schwiegershausen, Peter Pirsch. eurodac 1995: 8-13 [doi]

A system level design methodology for the optimization of heterogeneous multiprocessorsMarkus Schwiegershausen, Peter Pirsch. isss 1995: 162-169 [doi]

The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniquesMirjam Schönfeld, Jens Franzen, Markus Schwiegershausen, Peter Pirsch, Uwe Vehlies, Andreas Münzner. vlsisp, 11(1-2):51-74, 1995. [doi]

1991

Synthesis of intermediate memories for the data supply to processor arraysMirjam Schönfeld, Markus Schwiegershausen, Peter Pirsch. ccc 1992: 365-370

Synthesis of Intermediate Memories needed for the Data Supply to Processor ArraysMirjam Schönfeld, Markus Schwiegershausen, Peter Pirsch. vlsi 1992: 297-306

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