Table of Contents

• A Visual Computing Environment for Very Large Scale Biomolecular ModelingMichael Zeller, James C. Phillips, A. Dalke, W. Humphrey, Klaus Schulten, Thomas S. Huang, Vladimir Pavlovic, Yunxin Zhao, Zion Lo, Stephen M. Chu, Rajeev Sharma. 3 [doi]
• On Computing With Locally-Interconnected Architectures in Atomic/Nanoelectronic SystemsVwani P. Roychowdhury, M. P. Anantram. 14-23 [doi]
• Realization of a nonlinear digital filter on a DSP array processorHercule Kwan, Edward J. Powers, Earl E. Swartzlander Jr.. 24-33 [doi]
• A Linear Array Parallel Image Processor: SliM-IIHyunman Chang, Soohwan Ong, Myung Hoon Sunwoo. 34-41 [doi]
• A massively parallel implementation of the watershed based on cellular automataD. Noguet. 42-52 [doi]
• A strategy for determining a Jacobi specific dataflow processorEdwin Rijpkema, Gerben J. Hekstra, Ed F. Deprettere, Jun Ma. 53 [doi]
• Array Placement for Storage Size Reduction in Embedded Multimedia SystemsEddy de Greef, Francky Catthoor, Hugo De Man. 66-75 [doi]
• Buffer size optimization for full-search block matching algorithmsYuan-Hau Yeh, Chen-Yi Lee. 76-85 [doi]
• A VLSI Architecture for Image Geometrical Transformations Using an Embedded Core Based ProcessorCarolina Miro, Nicolas Darbel, Renaud Pacalet, Valerie Paquet. 86-95 [doi]
• A flexible data-interlacing architecture for full-search block-matching algorithmYeong-Kang Lai, Liang-Gee Chen, Yung-Pin Lee. 96 [doi]
• New arithmetic coder/decoder architectures based on pipeliningRoberto R. Osorio, Javier D. Bruguera. 106-115 [doi]
• Processor Elements for the Standard Cell Implementation of Residue Number SystemsAnsgar Drolshagen, H. Henkelmann, Walter Anheier. 116-123 [doi]
• Low latency word serial CORDICJulio Villalba, Tomás Lang. 124-131 [doi]
• CORDIC-based computation of arccos and arcsinTomás Lang, Elisardo Antelo. 132-143 [doi]
• Accurate Function Approximations by Symmetric Table Lookup and AdditionMichael J. Schulte, James E. Stine. 144-153 [doi]
• Low Power CORDIC Implementation Using Redundant Number RepresentationChristian V. Schimpfle, Sven Simon, Josef A. Nossek. 154-161 [doi]
• Efficient Implementation of Rotation Operations for High Performance QRD-RLS FilteringB. Haller, J. Goetze, Joseph R. Cavallaro. 162 [doi]
• A logical framework to prove properties of Alpha programsLuc Bougé, David Cachera. 187-198 [doi]
• Determination of the Processor Functionality in the Design of Processor ArraysDirk Fimmel, Renate Merker. 199-208 [doi]
• Three-dimensional orthogonal tile sizing problem: mathematical programming approachRumen Andonov, Nicola Yanev, Hafid Bourzoufi. 209-218 [doi]
• Scheduling in Co-Partitioned Array ArchitecturesUwe Eckhardt, Renate Merker. 219-228 [doi]
• Tiling with limited resourcesPierre-Yves Calland, Jack Dongarra, Yves Robert. 229-238 [doi]
• Libraries of schedule-free operators in AlphaFlorent de Dinechin. 239 [doi]
• Optimized software synthesis for synchronous dataflowShuvra S. Bhattacharyya, Praveen K. Murthy, Edward A. Lee. 250-262 [doi]
• The Processing Graph Method Tool (PGMT)Richard S. Stevens. 263-271 [doi]
• Algorithm and architecture-level design space exploration using hierarchical data flowsHelvio P. Peixoto, Margarida F. Jacome. 272-282 [doi]
• Mapping multirate dataflow to complex RT level hardware modelsJens Horstmannshoff, Thorsten Grötker, Heinrich Meyr. 283 [doi]
• Heterogeneous Multiprocessor Scheduling and Allocation using Evolutionary AlgorithmsCarsten Reuter, Markus Schwiegershausen, Peter Pirsch. 294-303 [doi]
• A Methodology for User-Oriented Scalability AnalysisDolors Royo, Miguel Valero-García, Antonio González, Carme Mari. 304-315 [doi]
• Performance model of the Argonne Voyager multimedia serverTerry Disz, Robert Olson, Rick L. Stevens. 316-327 [doi]
• PART: a partitioning tool for efficient use of distributed systemsJian Chen, Valerie E. Taylor. 328-337 [doi]
• An Approach for Quantitative Analysis of Application-Specific Dataflow ArchitecturesBart Kienhuis, Ed F. Deprettere, Kees A. Vissers, Pieter van der Wolf. 338-349 [doi]
• Automatic data mapping of signal processing applicationsCorinne Ancourt, Denis Barthou, Christophe Guettier, François Irigoin, Bertrand Jeannet, Jean Jourdan, Juliette Mattioli. 350 [doi]
• Configurable computing: the catalyst for high-performance architecturesCarl Ebeling, Darren C. Cronquist, Paul Franklin. 364-373 [doi]
• Fast Arithmetic and Fault Tolerance in the FERMI SystemLuca Breveglieri, Luigi Dadda, Vincenzo Piuri. 374-383 [doi]
• A Multiprocessor System for Real Time High Resolution Image CorrelationM. Cavadini, M. Wosnitza, Markus Thaler, Gerhard Tröster. 384-391 [doi]
• A Novel Sequencer Hardware for Application Specific ComputingReiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger. 392-401 [doi]
• A FPGA-based Implementation of an Intravenous Infusion Controller SystemCristiano C. de Araujo, Marcus V. D. dos Santos, Edna Barros. 402-411 [doi]
• Conception and design of a RISC CPU for the use as embedded controller within a parallel multimedia architectureStephanie Dogimont, M. Gumm, Friederich Mombers, Daniel Mlynek, A. Torielli. 412-421 [doi]
• A dedicated circuit for charged particles simulation using the Monte Carlo methodAndy Negoi, Alain Guyot, Jacques Zimmermann. 422-431 [doi]
• A Modular Element for Shared Buffer ATM Switch FabricsMike Parks. 432 [doi]
• A Datapath Generator for Full-Custom Macros of Iterative Logic ArraysMichael Gansen, Frank Richter, Oliver Weiss, Tobias G. Noll. 438-447 [doi]
• On core and more: a design perspective for systems-on-a-chipStefan Pees, Martin Vaupel, Vojin Zivojnovic, Heinrich Meyr. 448-457 [doi]
• ADPCM codec: from system level description to versatile HDL modelHerbert Dawid, Klaus-Jürgen Koch, Johannes Stahl. 458-467 [doi]
• Design methodology for digital signal processingGerhard Fettweis. 468 [doi]
• A flexible VLSI architecture for variable block size segment matching with luminance correctionPeter M. Kuhn, Andreas Weisgerber, Robert Poppenwimmer, Walter Stechele. 479-488 [doi]
• Implementation of Orthogonal Wavelet Transforms and their ApplicationsPeter Rieder, Josef A. Nossek. 489-498 [doi]
• An efficient architecture for the in place fast cosine transformManuel Sánchez, Juan López, Oscar G. Plata, Emilio L. Zapata. 499-508 [doi]
• An efficient video decoder design for MPEG-2 MP@MLJui-Hua Li, Nam Ling. 509-518 [doi]
• An Optimized Coefficient Update Processor for High-Throughput Adaptive EqualizersChristian Luetkemeyer. 519-528 [doi]
• Discrete Lagrangian Method for Optimizing the Design of Multiplierless QMF Filter BanksBenjamin W. Wah, Yi Shang, Zhe Wu. 529 [doi]