Table of Contents

• Design and Test: What Will It Take to Tie the Knot?Joseph B. Costello. 18
• Automotive Industry: The Next DFT ChallengeMichael S. Ledford. 19
• A Universal Framework for Managed Built-in TestColin Maunder. 21-29
• The Impact of Commercial Off-The-Shelf (COTS) Equipment on System Test and DiagnosisWilliam R. Simpson, John W. Sheppard. 30-36
• Experience in Diagnosing a Remote, Tele-Controlled Unit Using the AITEST Expert SystemIsrael Beniaminy, Moshe Ben-Bassat, M. Bodenheimer, M. Eshel. 37-44
• System Level Interconnect Test in a Tristate EnvironmentFrank W. Angelotti, Wayne A. Britson, Kerry T. Kaliszewski, Steve M. Douskey. 45-53
• Fast and Accurate CMOS Bridging Fault SimulationJeff Rearick, Janak H. Patel. 54-62
• Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate LogicPeter C. Maxwell, Robert C. Aitken. 63-72
• Test Generation with High Coverages for Quiescent Current Test of Bridging Faults in Combinational CircuitsEugeni Isern, Joan Figueras. 73-82
• CMOS Bridges and Resistive Transistor Faults: I::DDQ:: versus Delay EffectsHeinrich Theodor Vierhaus, Wolfgang Meyer, Uwe Gläser. 83-91
• Automated Wafer Lot Approval: A Statistically Based ImplementationKurt A. Milne. 92-98
• Practical Application of Statistical Process Control in Semiconductor ManufacturingBrian Beck. 99-107
• Application of Statistical Techniques to Critical System ParametersRick Boyle, Jack Donovan, Eugene R. Hnatek, Alex M. Ijaz. 108-114
• Parameter Monitoring: Advantages and PitfallsM. M. A. van Rosmalen, Keith Baker, Eric Bruls, Jochen A. G. Jess. 115-124
• Creating A Mixed-Signal Simulation Capability for Concurrent IC Design and Test Program DevelopmentTom Austin. 125-132
• Tools and Techniques for Converting Simulation Models into Test PatternsTony Taylor. 133-138
• Automatic Test Plan Generation for Analog and Mixed Signal Integrated Circuits using Partial Activation and High Level SimulationRavindranath Naiknaware, G. N. Nandakumar, Srinivasa Rao Kasa. 139-148
• Visualizing Test Information: A Novel Approach for Improving TestabilityJan Moorman, Steven D. Millman. 149-156
• Technology Independent Boundary Scan Synthesis (Technology and Physical Issues)Markus Robinson, Frederic Mailhot, Jim Konsevich. 157-166
• Utilizing Boundary Scan to Implement BISTTom Langford. 167-173
• Using Boundary Scan Test to Test Random Access Memory ClustersMath Muris, Alex S. Biewenga. 174-179
• On the Evaluation of Software Inspections and TestsJarir K. Chaar, Michael J. Halliday, Inderpal S. Bhandari, Ram Chillarege. 180-189
• On the Design for Testability of Communication SoftwareSamuel T. Chanson, Antonio Alfredo Ferreira Loureiro, Son T. Vuong. 190-199
• Certification Trails and Software Design for TestabilityGregory F. Sullivan, Dwight S. Wilson, Gerald M. Masson. 200-209
• Economics Modelling for the Determination of Test Strategies for Complex VLSI BoardsChryssa Dislis, J. H. Dick, I. D. Dear, I. N. Azu, Anthony P. Ambler. 210-217
• The Economics of Guardband PlacementRichard H. Williams, Charles F. Hawkins. 218-225
• Implementation of Parallelsite Test on an 8Bit Configurable MicrocontrollerDouglas J. Mirizzi, Willie Jerrels, Dale Ohmart. 226-235
• BIST and Delay Fault DetectionSlawomir Pilarski, Alicja Pierzynska. 236-242
• Delay Testing Using a Matrix of Accessible StoragePrab Varma, Tushar Gheewala. 243-252
• A Method for Delay Fault Self-Testing of MacrocellsHarold N. Scholz, Duane R. Aadsen, Yervant Zorian. 253-261
• Position Statement: ITC93 Boundary-Scan PanelColin Maunder. 262
• Benefits of Boundary-Scan to In-Circuit TestDavid A. Greene. 263
• IEEE 1149.1 Growing PainsWayne T. Daniel. 264
• IEEE 1149.1: How to Justify ImplementationMick Tegethoff. 265
• Known Godd Die for MCMs: Enabling TechnologiesDavid C. Keezer. 266
• Scan DFT: Why More Can Cost LessPrab Varma. 267
• Testing Fully Testable Systems: A Case StudyJohn W. Sheppard. 268
• DFT: Profit or Loss -- A Position PaperJon Turino. 269
• Cultural Evolution in Software TestingAlex Elentukh. 270
• Software Regression Testing Success StoryMichael A. Long. 271-272
• The Evolving Role of Testing in Open Systems StandardsJames F. Leathrum, K. A. Liburdy. 273-274
• Very-Low-Voltage Testing for Weak CMOS Logic ICsHong Hao, Edward J. McCluskey. 275-284
• The Cost of Quality: Reducing ASIC Defects with I::DDQ:: At-Speed Testing and Increased Fault CoverageRick Gayle. 285-292
• A Comparison of Stuck-At Fault Coverage and I::DDQ:: Testing on Defect LevelsPaul C. Wiscombe. 293-299
• Towards a Test Standard for Board and System Level Mixed-Signal InterconnectsCarl W. Thatcher, Rodham E. Tulloss. 300-308
• Structure and Metrology for an Analog Testability BusKenneth P. Parker, John E. McDermid, Stig Oresjo. 309-322
• Control and Observation of Analog Nodes in Mixed-Signal BoardsJosé Silva Matos, Ana C. Leão, João Canas Ferreira. 323-331
• Structured CBIST in ASICsRobert Gage. 332-338
• BIST for Embedded Static RAMs with Coverage CalculationJos van Sas, Geert van Wauwe, Erik Huyskens, Dirk Rabaey. 339-348
• An ALU-Based Programmable MISR/Pseudorandom Generator for a MC68HC11 Family Self-TestJames Broseghini, Donald H. Lenhert. 349-358
• A Test Methodology for VLSI Chips on SiliconThomas M. Storey. 359-368
• MCM Foundry Test Methodology and ImplementationLynn Roszel. 369-372
• Design-For-Test Techniques Utilized in an Avionics Computer MCMRussell J. Wagner, Joel A. Jorgenson. 373-382
• Algorithms for Cost Optimised Test Strategy SelectionChryssa Dislis, J. H. Dick, Anthony P. Ambler. 383-391
• IRIDIUM:::tm::: Satellite: A Large System Application of Design for TestabilityCary Champlin. 392-398
• IEEE 1149 Standards - Changing Testing, Silicon to SystemsRodham E. Tulloss. 399-408
• Distributed Implementation of an ATPG System Using Dynamic Fault AllocationM. J. Aguado, E. de la Torre, Miguel Miranda, C. López-Barrio. 409-418
• Workstation Based Parallel Test GenerationRobert H. Klenke, Lori M. Kaufman, James H. Aylor, Ronald Waxman, Padmini Narayan. 419-428
• A Method for Reducing the Search Space in Test Pattern GenerationMitsuo Teramoto. 429-435
• Extraction of Coupled SPICE Models for Packages and InterconnectsScott Diamond, Bo Janko. 436-445
• Keep Alive - A New Requirement for High Performance uProcessor TestRudy Garcia. 446-450
• Minimizing Test Time by Exploiting Parallelism in Macro TestHans Bouwmeester, Steven Oostdijk, Frank Bouwman, Rudi Stans, Loek Thijssen, Frans P. M. Beenker. 451-460
• A Flexible Approach to Data Collection for Component Test SystemsJim Mosley III. 461-470
• Generated in Real-time Instant Process Statistics ( GRIPS ): Immediate, Tester-computed Test Statistics, Eliminating the Post-processing of DatalogsJohn O Donnell. 471-477
• Realizing a High Measure of Confidence for Defect Level Analysis of Random TestingParesh Gondalia, Allan Gutjahr, Wen-Ben Jone. 478-487
• Partial Scan at the Register-Transfer LevelJohannes Steensma, Francky Catthoor, Hugo De Man. 488-497
• Partial Scan Using Reverse Direction Empirical TestabilityKee Sup Kim, Charles R. Kime. 498-506
• PSBIST: A Partial-Scan Based Built-In Self-Test SchemeChih-Jen Lin, Yervant Zorian, Sudipta Bhawmik. 507-516
• Hierarchically Accessing 1149.1 Applications in a System EnvironmentLee Whetsel. 517-526
• IEEE P1149.5 to 1149.1 Data and Protocol ConversionChristopher Poirier. 527-535
• BIST for 1149.1-Compatible Boards: A Low-Cost and Maximum-Flexibility SolutionJosé M. M. Ferreira, Manuel G. Gericota, José L. Ramalho, Gustavo R. Alves. 536-543
• A Novel Instrument for Accurate Time Measurement in Automatic Calibration of Test SystemsRichard K. Feldman. 544-551
• Timing Analyzer for Embedded TestingArnold Frisch, Thomas Almy. 552-555
• Characterization of Edge Placement Accuracy in High-Speed Digital Pin ElectronicsWill Creek. 556-565
• Fault Coverage of DC Parametric Tests for Embedded Analog AmplifiersMani Soma. 566-573
• Catch the Ground Bounce Before It Hits your SystemE. Kurzweil, M. Lallement, R. Blanc, R. Pasquinelli. 574-584
• Integrating Electrical Test into Final AssemblyHugh Littlebury, Roger Brueckner. 585-589
• Design-For-Testability EconomicsCarl W. Thatcher. 590
• Practical Considerations for Mixed-Signal Test BusNai-Chi Lee. 591-592
• Test Synthesis from a User PerspectiveGunnar Carlsson. 593
• DOs and DON Ts in Computing Fault CoverageMiron Abramovici. 594
• Let s Grade ALL the FaultsPeter C. Maxwell. 595
• Quality Testing Requires Quality ThinkingJerry M. Soden, Charles F. Hawkins. 596
• Quality and Single-Stuck FaultsEdward J. McCluskey. 597
• Test Pattern Generation with RestrictorsM. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor. 598-605
• CHEETA: Composition of Hierarchical Sequential Tests Using ATKETPraveen Vishakantaiah, Jacob A. Abraham, Daniel G. Saab. 606-615
• Switch-Level ATPG Using Constraint-Guided Line JustificationEun Sei Park, M. Ray Mercer. 616-625
• i::DD:: Pulse Response Testing of Analog and Digital CMOS CircuitsJ. S. Beasley, H. Ramamurthy, Jaime Ramírez-Angulo, Mark DeYong. 626-634
• Built-In Current Sensor for I::DDQ:: Test in CMOSChing-Wen Hsue, Chih-Jen Lin. 635-641
• A General Purpose I::DDQ:: Measurement CircuitKenneth M. Wallquist, Alan W. Righter, Charles F. Hawkins. 642-651
• Analog Circuit Testing Based on Sensitivity Computation and New Circuit ModelingNaim Ben Hamida, Bozena Kaminska. 652-661
• Multiple Fault Diagnosis in Printed Circuit BoardsS. J. Barnfield, W. R. Moore. 662-671
• The Standard Mirror Boards (SMBs) ConceptChristophe Vaucher, Louis Balme. 672-679
• Fault Diagnosis of Flash ADC using DNL TestAnchada Charoenrook, Mani Soma. 680-689
• FFT Based Troubleshooting of 120dB Dynamic Range ADC SystemsDavid Ownby, Harold Bogard. 690-696
• A New Approach for PLL Characterization on Mixed Signal ATEShinichi Kimura, Makoto Kimura, Takayuki Nakatani, Masao Sugai. 697-704
• An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold CalculationD. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch. 705-713
• Generation of Compact Delay Tests by Multiple-Path ActivationSoumitra Bose, Prathima Agrawal, Vishwani D. Agrawal. 714-723
• A Method to Derive Compact Test Sets for Path Delay Faults in Combinational CircuitsJayashree Saxena, Dhiraj K. Pradhan. 724-733
• Synthesizing for Scan Dependence in Built-In Self-Testable DesingsLaNae J. Avra, Edward J. McCluskey. 734-743
• A Conditional Resource-Sharing Method for Behavior Synthesis of Highly- Testable Data PathsTien-Chien Lee, Niraj K. Jha, Wayne Wolf. 744-753
• A Synthesis Approach to Design for TestabilitySuman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal. 754-763
• Test Features of the HP PA7100LC ProcessorDon Douglas Josephson, Daniel J. Dixon, Barry J. Arnold. 764-772
• Testability Features of the SuperSPARC:::tm:::Rajiv Patel, Krishna Yarlagadda. 773-781
• VINCI: Secure Test of a VLSI High-Speed Encryption SystemH. Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, R. Zimmermann, Wolfgang Fichtner. 782-790
• A Built-in Self- Test for ADC and DAC in a Single-Chip Speech CODECEiichi Teraoka, Toru Kengaku, Ikuo Yasui, Kazuyuki Ishikawa, Takahiro Matsuo, Hideyuki Wakada, Narumi Sakashita, Yukihiko Shimazu, Takeshi Tokuda. 791-796
• Design for Testability of a Modular, Mixed Signal Family of VLSI DevicesEd Flaherty, Andrew Allen, John Morris. 797-804
• A BIST Scheme for an SNR Test of a Sigma-Delta ADCM. F. Toner, Gordon W. Roberts. 805-814
• Development of Fault Model and Test Algorithms for Embedded DRAMsManoj Sachdev, Math Verstraelen. 815-824
• Fault Location Algorithms for Repairable EmbeddedRobert P. Treuer, Vinod K. Agarwal. 825-834
• In System Transparent Autodiagnostics of RamsJanusz Sosnowski. 835-844
• Mutation-Based Testing of Concurrent ProgramsRichard H. Carver. 845-853
• Automated Testing of Open Software StandardsJames F. Leathrum, K. A. Liburdy. 854-858
• Efficient Testing of Software ModificationsAnneliese Amschler Andrews, Kurt M. Olender. 859-864
• Analyss of Dynamic Effects of Resistive Bridging Faults in CMOS and BiCMOS Digital ICsMichele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò. 865-874
• On Accurate Modeling and Efficient Simulation of CMOS OpensChennian Di, Jochen A. G. Jess. 875-882
• Simulation of non-classical Faults on the Gate Level - The Fault Simulator COMISM -Udo Mahlstedt, Jürgen Alt. 883-892
• Differential Virtual Instrumentation with ContinuouslyBryan J. Dinteman, Paul Botsford. 893-901
• Testable Programmable Digital Clock Pulse Control ElementsKenneth D. Wagner, Bernd Könemann. 902-909
• Knowledge-Based TestingHimanshu Kumar, Scott A. Erjavic. 910-917
• High-Speed Sampling Capability for a VLSI Mixed-Signal TesterPaul Sakamoto, Tom Chiu. 918-927
• CAD-Driven High-Precision E-Beam PositioningKent Kwang, Hsin Wang, Arthur Hu, Mitsuyuki Asaki, Hironobu Niijima. 928-935
• Terminating Transmission lines in the Test EnvironmentRichard F. Herlein. 936-944
• Mix Test: A Mixed-Signal Extension to a Digital Test SystemR. Mehtani, B. Atzema, M. De Jonghe, Richard Morren, Geert Seuren, Taco Zwemstra. 945-953
• Delay Testing for Non-Robust Untestable CircuitsKwang-Ting Cheng, Hsi-Chuan Chen. 954-961
• Design of Scan-Based Path-Delay-Testable Sequential CircuitsAnkan K. Pramanick, Sandip Kundu. 962-971
• DELTEST: Deterministic Test Generation for Gate-Delay FaultsUdo Mahlstedt. 972-980
• A Serial-Scan Test-Vector-Compression MethodologyChauchin Su, Kychin Hwang. 981-988
• Multiconfiguration Technique to Reduce Test Duration for Sequential CircuitsYves Bertrand, Frédéric Bancel, Michel Renovell. 989-997
• A Learning-Based Method to Match a Test Pattern Generator to a Circuit-Under-TestIrith Pomeranz, Sudhakar M. Reddy. 998-1007
• On Selecting Flip-Flops for Partial ResetMiron Abramovici, Prashant S. Parikh, Ben Mathew, Daniel G. Saab. 1008-1012
• Inhomogeneous Cellular Automata for Weighted-Random-Pattern GenerationDanial J. Neebel, Charles R. Kime. 1013-1022
• Generation of Optimized Single Distributions of Weights for Random Built-in Self-TestMiguel Miranda, Carlos A. López-Barrio. 1023-1030
• Calculatoin of Multiple Sets of Weights for Weighted-Random TestingMichael Bershteyn. 1031-1040
• Novel Test Pattern Generators for Pseudo-Exhaustive TestingRajagopalan Srinivasan, Sandeep K. Gupta, Melvin A. Breuer. 1041-1050
• BP-1992 A Comparison of Defect Models for Fault Location with I::DDQ:: MeasurementsRobert C. Aitken. 1051-1060