Prab Varma - researchr alias

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Viewing Publication 1 - 23 from 23

2016

Welcome MessagePrab Varma, Miroslav N. Velev. hldvt 2016: 1 [doi]

2012

Current and Future Directions in Automatic Test Pattern Generation for Power Delivery Network ValidationPrab Varma. ats 2012: 233-238 [doi]

2004

Verification evolution or industrial revolution?Prab Varma. dt, 21(2):168, 2004.

2003

Design Verification Problems: Test To The Rescue?Prab Varma. itc 2003: 1292 [doi]

2001

ATPG for Design Errors-Is It Possible?Magdy S. Abadir, Scott Davidson, Vijay Nagasamy, Dhiraj K. Pradhan, Prab Varma. vts 2001: 283-285 [doi]

2000

Test Cycle Count Reduction in a Parallel Scan BIST EnvironmentBechir Ayari, Prab Varma. et, 16(5):409-418, 2000. [doi]

1998

Test Cycle Count Reduction in a Parallel Scan BIST EnvironmentBechir Ayari, Prab Varma. ats 1998: 21-26 [doi]

A structured test re-use methodology for core-based system chipsPrab Varma, Sandeep Bhatia. itc 1998: 294-302 [doi]

System chip test: are we there yet?Prab Varma. itc 1998: 1144 [doi]

System Chip Test Challenges, Are There Solutions Today? (Panel)Prab Varma. dac 1998: 750-751 [doi]

1997

Test Compaction in a Parallel Access Scan EnvironmentSandeep Bhatia, Prab Varma. ats 1997: 300-305 [doi]

1996

A Unifying Methodology for Intellectual Property and Custom Logic TestingSandeep Bhatia, Tushar Gheewala, Prab Varma. itc 1996: 639-648

Delay Fault Testing: How Robust are Our Models?Sandeep K. Gupta, Slawomir Pilarski, Sudhakar M. Reddy, Jacob Savir, Prab Varma. vts 1996: 502-503 [doi]

1995

Optimizing Product Profitability - The Test WayPrab Varma. itc 1995: 922

1994

The economics of scan-path design for testabilityPrab Varma, Tushar Gheewala. et, 5(2-3):179-193, 1994. [doi]

On Path-Delay Testing in a Standard Scan EnvironmentPrab Varma. itc 1994: 164-173

1993

Delay Testing Using a Matrix of Accessible StoragePrab Varma, Tushar Gheewala. itc 1993: 243-252

Scan DFT: Why More Can Cost LessPrab Varma. itc 1993: 267

1992

On test generation for path delay faults in ASICsPrab Varma. vts 1992: 19-24 [doi]

1990

TDRC-a symbolic simulation based design for testability rules checkerPrab Varma. itc 1990: 1055-1064 [doi]

1988

A knowledge-based test generator for standard cell and iterative array logic circuitsPrab Varma, Yoshihiro Tohma. jssc, 23(2):428-436, April 1988. [doi]

1987

A Fast Signature Simulation Tool for Built-In Self-Testing CircuitsS. B. Tan, K. Totton, Keith Baker, Prab Varma, R. Porter. dac 1987: 17-25 [doi]

1984

An Analysis of the Economics of Self TestPrab Varma, Anthony P. Ambler, Keith Baker. itc 1984: 20-30

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