Abstract is missing.
- Emerging Technologies Drive Domain-Specific SolutionsWalden C. Rhines. 10
- New and Not-So-New Test Challenges of the Next DecadeWojciech Maly. 11
- Test Generation for Ultra-Large Circuits Using ATPG Constraints and Test-Pattern TemplatesPeter Wohl, John A. Waicukauski. 13-20
- Test Pattern Generation for Circuits with Asynchronous Signals Based on ScanMitsuo Teramoto, Tomoo Fukazawa. 21-28
- Accelerated Compact Test Set Generation for Three-State CircuitsM. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor. 29-38
- Comparing Topological, Symbolic and GA-based ATPGs: An Experimental ApproachFulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda. 39-47
- BIST Fault Diagnosis in Scan-Based VLSI EnvironmentsYuejian Wu, Saman Adham. 48-57
- LFSR Reseeding as a Component of Board Level BISTPieter M. Trouborst. 58-67
- Using ILA Testing for BIST in FPGAsCharles E. Stroud, Eric Lee, Srinivasa Konala, Miron Abramovici. 68-75
- An Effective BIST Scheme for DatapathsDimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian. 76-85
- Four Multi Probing Test for 16 Bit DAC with Vertical Contact Probe CardSeiji Sasho, Teruhisa Sakata. 86-91
- A Demonstration IC for the P1149.4 Mixed-Signal Test StandardKeith Lofstrom. 92-98
- Testing the Digital Modulation of PHS DevicesKoji Asami. 99-103
- Testing and Characterizing Jitter in 100BASE-TX and 155.52 Mbit/S ATM Devices with a 1 Gsample/s AWG in an ATE SystemBarry D. Kulp. 104-111
- High-Speed I::DDQ:: Measurement CircuitKenji Isawa, Yoshihiro Hashimoto. 112-117
- Extending Calibration IntervalsSolomon Max. 118-126
- Manufacturing Test of Fiber Channel Communications Cards and Optical SubassembliesSteven DeFoster, Dennis Karst, Matthew Peterson, Paul Sendelbach, Kirk Kottschade. 127-134
- A Universal Technique for Accelerating Simulation of Scan Test PatternsBejoy G. Oomman, Wu-Tung Cheng, John A. Waicukauski. 135-141
- On Potential Fault Detection in Sequential CircuitsElizabeth M. Rudnick, Janak H. Patel, Irith Pomeranz. 142-149
- Improving Gate Level Fault Coverage by RTL Fault GradingWeiwei Mao, Ravi K. Gulati. 150-159
- Distributed Mixed Level Logic and Fault Simulation on the Pentium® Pro MicroprocessorSankaran Karthik, Mark Aitken, Glidden Martin, Srinivasu Pappula, Bob Stettler, Praveen Vishakantaiah, Manuel A. d Abreu, Jacob A. Abraham. 160-166
- Altering a Pseudo-Random Bit Sequence for Scan-Based BISTNur A. Touba, Edward J. McCluskey. 167-175
- MFBIST: A BIST Method for Random Pattern Resistant CircuitsMohammed F. AlShaibi, Charles R. Kime. 176-185
- Two-Dimensional Test Data Decompressor for Multiple Scan DesignsNadime Zacharia, Janusz Rajski, Jerzy Tyszer, John A. Waicukauski. 186-194
- Mixed-Mode BIST Using Embedded ProcessorsSybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig. 195-204
- Test Quality of Asynchronous Circuits: A Defect-oriented EvaluationMarly Roncken, Eric Bruls. 205-214
- Optimal Scan for Pipelined Testing: An Asynchronous FoundationMarly Roncken, Emile H. L. Aarts, Wim F. J. Verhaegh. 215-224
- An Asynchronous Scan Path Concept for Micropipelines using the Bundled Data ConventionVolker Schöber, Thomas Kiel. 225-231
- Synthesis-for-Initializability of Asynchronous Sequential MachinesMontek Singh, Steven M. Nowick. 232-241
- Burn-in Elimination of a High Volume Microprocessor Using I::DDQ::Timothy R. Henry, Thomas Soo. 242-249
- I::DDQ:: and AC Scan: The War Against Unmodelled DefectsPeter C. Maxwell, Robert C. Aitken, Kathleen R. Kollitz, Allen C. Brown. 250-258
- High Resolution I::DDQ:: Characterization and Testing - Practical IssuesAlan W. Righter, Jerry M. Soden, Richard W. Beegle. 259-268
- Novel Optical Probing System with Submicron Spatial Resolution for Internal Diagnosis of VLSI CircuitsK. Ozaki, H. Sekiguchi, S. Wakana, Y. Goto, Y. Umehara, J. Matsumoto. 269-275
- An Exact Non-Enumerative Fault Simulator for Path-Delay FaultsMarwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal. 276-285
- A Diagnostic ATPG for Delay Faults Based on Genetic AlgorithmsPatrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez. 286-293
- Diagnostic Fault Equivalence Identification Using Redundancy Information and Structural AnalysisIsmed Hartanto, Vamsi Boppana, W. Kent Fuchs. 294-302
- Self-Learning Signature Analysis for Non-Volatile Memory TestingPiero Olivo, Marcello Dalpasso. 303-308
- Weak Write Test Mode: An SRAM Cell Stability Design for Test TechniqueAnne Meixner, Jash Banik. 309-318
- A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAMNarumi Sakashita, Fumihiro Okuda, Ken ichi Shimomura, Hiroki Shimano, Mitsuhiro Hamada, Tetsuo Tada, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe. 319-324
- Analog/Digital Testing of Loaded Boards Without Dedicated Test PointsChristophe Vaucher, Louis Balme. 325-332
- Opens Board Test Coverage: When is 99 Really 40 ?Mick Tegethoff, Kenneth P. Parker, Ken Lee. 333-339
- A Roadmap for Boundary-Scan Test ReuseD. Eugene Wedge, Tom Conner. 340-346
- Local Transformations and Robust Dependent Path DelayHarry Hengster, Uwe Sparmann, Bernd Becker, Sudhakar M. Reddy. 347-356
- On Cancelling the Effects of Logic Sharing for Improved Path Delay Fault TestabilityIrith Pomeranz, Sudhakar M. Reddy. 357-366
- Detecting Delay Flaws by Very-Low-Voltage TestingJonathan T.-Y. Chang, Edward J. McCluskey. 367-376
- Testability Features for a Submicron Voice-coder ASICF. Pichon. 377-385
- A BIST Methodology for Comprehensive Testing of RAM with Reduced Heat DissipationHugo Cheung, Sandeep K. Gupta. 386-395
- DFT Strategy for Intel MicroprocessorsWayne M. Needham, Naga Gollakota. 396-399
- Proposal to Simplify Development of a Mixed-Signal Test StandardLee Whetsel. 400-409
- A Method of Extending an 1149.1 Bus for Mixed-Signal TestingRobert J. Russell. 410-416
- Early Capture for Boundary Scan Timing MeasurementsKeith Lofstrom. 417-422
- Identification and Test Generation for Primitive FaultsAngela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar. 423-432
- Test Generation for Global Delay FaultsG. M. Luong, D. M. H. Walker. 433-442
- ATPD: An Automatic Test Pattern Generator for Path Delay FaultsDimitrios Karayiannis, Spyros Tragoudas. 443-452
- Scan Design Oriented Test Technique for VLSI s Using ATEYasuji Oyama, Toshinobu Kanai, Hironobu Niijima. 453-460
- Virtual Test of Noise and Jitter ParametersKlaus Helmreich, G. Reinwardt. 461-470
- A Novel Approach to the Analysis of VLSI Device Test ProgramsYuhai Ma, Wanchun Shi. 471-480
- Digital Integrated Circuit Testing using Transient Signal AnalysisJames F. Plusquellic, Donald M. Chiarulli, Steven P. Levitan. 481-490
- Towards an Effective I::DDQ:: Test Vector Selection and Application MethodologyJos van Sas, Urbain Swerts, Marc Darquennes. 491-500
- Correlating Defects to Functional and I::DDQ:: TestsTheo J. Powell, James R. Pair, Bernard G. Carbajal III. 501-510
- Defect-Oriented vs. Schematic-Level Based Fault Simulation for Mixed-Signal ICsThomas Olbrich, Jordi Pérez, Ian A. Grout, Andrew M. D. Richardson, Carles Ferrer. 511-520
- Hierarchy Based Statistical Fault Simulation of Mixed-Signal ICsGiri Devarayanadurg, Prashant Goteti, Mani Soma. 521-527
- An Integration of Memory-Based Analog Signal Generation into Current DFT ArchitecturesEvan M. Hawrysh, Gordon W. Roberts. 528-537
- Partial Scan Design Based on State Transition ModelingVamsi Boppana, W. Kent Fuchs. 538-547
- A Global Algorithm for the Partial Scan Design Problem Using Circuit State InformationDong Xiang, Janak H. Patel. 548-557
- Partial Scan Flip Flop Selection for Simulation-Based Sequential ATPGsFulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda. 558-564
- Standard Test Interface Language (STIL): A New Language for Patterns and WaveformsAnthony Taylor, Gregory A. Maston. 565-570
- LIMSoft: Automated Tool for Design and Test Integration of Analog CircuitsNaim Ben Hamida, Khaled Saab, David Marche, Bozena Kaminska, Guy Quesnel. 571-580
- Developing a Testing Maturity Model for Software Test Process Evaluation and ImprovementIlene Burnstein, Taratip Suwannasart, C. Robert Carlson. 581-589
- ASIC Yield Estimation at Early Design CycleVon-Kyoung Kim, Mick Tegethoff, Tom Chen. 590-594
- Risk Assessment Sampling Plans for Non-Standard (Maverick) MaterialDaniel P. Core. 595-604
- SPC on the IC-Production Test ProcessJos van der Peet, Ger van Boxem. 605-610
- Beyond the Byzantine Generals: Unexpected Behaviour and Bridging Fault DiagnosisDavid B. Lavo, Tracy Larrabee, Brian Chess. 611-619
- Defect-Oriented IC Test and Diagnosis Using VHDL Fault SimulationF. Celeiro, L. Dias, J. Ferreira, Marcelino B. Santos, João Paulo Teixeira. 620-628
- Using Target Faults To Detect Non-Tartget DefectsLi-C. Wang, M. Ray Mercer, Thomas W. Williams. 629-638
- A Unifying Methodology for Intellectual Property and Custom Logic TestingSandeep Bhatia, Tushar Gheewala, Prab Varma. 639-648
- Constructive Multi-Phase Test Point Insertion for Scan-Based BISTNagesh Tamarapalli, Janusz Rajski. 649-658
- Orthogonal Scan: Low-Overhead Scan for Data PathsRobert B. Norwood, Edward J. McCluskey. 659-668
- An Application of Photoconductive Switch for High-Speed TestingKazunori Chihara, Takashi Sekino, Koji Sasaki. 669-676
- Generation Technique of 500MHz Ultra-High Speed Algorithmic PatternHideaki Imada, Kenichi Fujisaki, Toshimi Ohsawa, Masaru Tsuto. 677-684
- The Effect of Periof Generation Techniques on Period Resolution and Waveform Jitter in VLSI Test SystemsMichael G. Davis. 685-690
- Analysis and Detection of Timing Failures in an Experimental Test ChipPiero Franco, Siyad C. Ma, Jonathan Chang, Yi-Chin Chu, Sanjay Wattal, Edward J. McCluskey, Robert L. Stokes, William D. Farwell. 691-700
- A Unique Methodology for At-Speed Test of cDSP:::TM::: and ASIC DevicesDavid Potts, Roger Griesmer. 701-707
- Cost Effective Frequency Measurement for Production TestingRalf Stoffels. 708-716
- Backplane Interconnect Test in a Boundary-Scan EnvironmentWuudiann Ke. 717-724
- Testability-Oriented Hardware/Software PartitioningYves Le Traon, Ghassan Al Hayek, Chantal Robach. 725-731
- System Level Fault SimulationPablo Sanchez, Isabel Hidalgo. 732-740
- ASIC BIST Synthesis: A VHDL ApproachTom Eberle, Robert McVay, Chris Meyers, Jason Moore. 741-750
- Integrating Scan into Hierarchical Synthesis MethodologiesJames Beausang, Chris Ellingham, Markus Robinson. 751-756
- Synthesis of Self-Testing Finite State Machines from High-Level SpecificationsVishwani D. Agrawal, Ronald D. Blanton, Maurizio Damiani. 757-766
- Fault Coverage Analysis for Physically-Based CMOS Bridging Faults at Different Power Supply VoltagesYuyun Liao, D. M. H. Walker. 767-775
- Realistic-Faults Mapping Scheme for the Fault Simulation of Integrated Analogue CMOS CircuitsMichael J. Ohletz. 776-785
- I::DDQ:: Test: Sensitivity Analysis of ScalingThomas W. Williams, Robert H. Dennard, Rohit Kapur, M. Ray Mercer, Wojciech Maly. 786-792
- Effects of Multi-Product, Small-Sized Production of LSIs Packaged in Various Packages on the Final Test Process Efficiency and CostHiromu Fujioka, Koji Nakamae, Akio Higashi. 793-799
- Issues in Optimizing the Test Process - A Telecom Case StudyFelix Frayman, Mick Tegethoff, Brenton White. 800-808
- Application of Boundary Scan in a Fault Tolerant Computer SystemMatthew Boutin, Peter Dziel. 809-817
- Optimal Multiple Chain Relay Testing Scheme for MCMs on Large Area SubstratesKoppolu Sasidhar, Abhijit Chatterjee, Yervant Zorian. 818-827
- Three Different MCMs, Three Different Test StrategiesAndrew Flint. 828-833
- MCM Compute Node Thermal Failure - Design or Test Problem?Edward P. Sayre. 834-838
- Commercial Design Verification: Methodology and ToolsCarl Pixley, Noel R. Strader, W. C. Bruce, Jaehong Park, Matt Kaufmann, Kurt Shultz, Michael Burns, Jainendra Kumar, Jun Yuan, Janet Nguyen. 839-848
- Formal Verification of the UltraSPARC:::TM::: Family of Processors via ATPG MethodsMarc E. Levitt. 849-856
- PowerPC:::TM::: Array Verification Methodology using Formal TechniquesNeeta Ganguly, Magdy S. Abadir, Manish Pandey. 857-864
- An ATPG-Based Framework for Verifying Sequential EquivalenceShi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Uwe Gläser. 865-874
- A Unified Framework for Design Validation and Manufacturing TestDinos Moundanos, Jacob A. Abraham, Yatin Vasant Hoskote. 875-884
- From Specification Validation to Hardware Testing: A Unified MethodGhassan Al Hayek, Chantal Robach. 885-893
- Testing-Based Analysis of Real-Time System ModelsDuncan Clarke, Insup Lee. 894-903
- Generation of Test Cases for Hardware Design Verification of a Super-Scalar Fetch ProcessorIrith Pomeranz, Nirmal R. Saxena, Richard Reeve, Paritosh Kulkarni, Yan A. Li. 904-913
- Process-Aggravated Noise (PAN): New Validation and Test ProblemsMelvin A. Breuer, Sandeep K. Gupta. 914-923
- Introduction ITC 1996 Lecture Series on Unpowered Opens TestingKenneth P. Parker. 924
- Capacitive Leadframe TestingTed T. Turner. 925
- High Fault Coverage of In-Circuit IC Pin Faults with a Vectorless Test Technique Using Parasitic TransistorsJack Ferguson. 926
- Two New Techniques for Identifying Opens on Printed Circuit Boards: Analog Junction Test, and Radio Frequency Induction TestJoe Wrinn. 927
- Analog AC Harmonic Method for Detecting Solder OpensAnthony J. Suto. 928
- Unpowered Opens Test with X-Ray LaminographyStig Oresjo. 929
- An Overview of CMOS VLSI Failure Analysis and the Importance of Test and DiagnosticsDavid P. Vallett. 930
- Modelling the Unmodellable: Algorithmic Fault DiagnosisRobert C. Aitken. 931
- Shmoo Plots - the Black Art of IC TestKeith Baker, Jos van Beers. 932-933
- Integrating Automated Diagnosis into the Testing and Failure Analysis OperationsKenneth M. Butler, Karl Johnson, Jeff Platt, Anjali Jones, Jayashree Saxena. 934
- IC Failure Analysis Tools and Techniques - Macig, Mystery, and ScienceJerry M. Soden, Richard E. Anderson, Christopher L. Henderson. 935
- Practical Issues of Failure Diagnosis and Analysis in a Fast Cycle Time EnvironmentDonald Staab. 936
- The Key to Concurrent Engineering is Design ToolsWilliam R. Simpson. 937
- The Return of Asynchronous LogicStephen B. Furber. 938
- Asynchronous Design: Working the Fast LaneMarly Roncken. 939
- Challenge of the 90 s: Testing CoreWare:::TM::: Based ASICsRochit Rajsuman. 940
- The Need for Complete System Level Test StandardizationPeter Dziel. 941
- Deep Sub-micron I::DDQ:: Test OptionsManoj Sachdev. 942