Theo J. Powell - researchr alias

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Viewing Publication 1 - 12 from 12

2006

Reducing Design Verification Cycle Time through Testbench RedundancyAman Kokrady, Theo J. Powell, S. Ramakrishnan. vlsid 2006: 243-248 [doi]

2005

Chasing subtle embedded RAM defects for nanometer technologiesTheo J. Powell, Amrendra Kumar, Joseph Rayhawk, Nilanjan Mukherjee. itc 2005: 9 [doi]

2003

BIST for Deep Submicron ASIC Memories with High Performance ApplicationTheo J. Powell, Wu-Tung Cheng, Joseph Rayhawk, Omer Samman, Paul Policke, Sherry Lai. itc 2003: 386-392 [doi]

2000

Delta Iddq for Testing ReliabilityTheo J. Powell, James R. Pair, Melissa St. John, Doug Counce. vts 2000: 439-443 [doi]

1997

A 256Meg SDRAM BIST for Disturb Test ApplicationTheo J. Powell, Dan Cline, Francis Hii. itc 1997: 200-208

1996

Correlating Defects to Functional and I::DDQ:: TestsTheo J. Powell, James R. Pair, Bernard G. Carbajal III. itc 1996: 501-510

Consistently dominant fault model for tristate buffer netsTheo J. Powell. vts 1996: 400-404 [doi]

1995

Test Generation and Design for Test for a Large Multiprocessing DSPGraham Hetherington, Greg Sutton, Kenneth M. Butler, Theo J. Powell. itc 1995: 149-156

1994

Correlating defect level to final test fault coverage for modular structured designs [microcontroller family]Theo J. Powell, Kenneth M. Butler, Mike Ales, Roy Haley, Mark Perry. vts 1994: 192-196 [doi]

1988

Testability Features in the TMS370 Family of MicrocomputersTheo J. Powell, Fred Hwang, Bill Johnson. itc 1988: 153-160

1982

Analysis and Simulation of Parallel Signature AnalyzersThirumalai Sridhar, D.-S. Ho, Theo J. Powell, Satish M. Thatte. itc 1982: 656-661

An Architecture for Testable VLSI ProcessorsSatish M. Thatte, D.-S. Ho, H.-T. Yuan, Thirumalai Sridhar, Theo J. Powell. itc 1982: 484-493

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