Abstract is missing.
- Business constraints drive test decisionsPaul Domino. 1 [doi]
- How are we going to test SOC's on a board?Michael J. Smith. 1 [doi]
- Achieving higher yield through diagnosisNagesh Tamarapalli. 1 [doi]
- Needs fabless yield ramp foundry partnership to be most successfulBruce Cory. 1 [doi]
- Reducing high-speed/RF test cost - guaranteed by design or guaranteed to fail?Mustapha Slamani. 1 [doi]
- Guaranteed by design or guaranteed to fail or guaranteed by test? or ... neither?Mani Soma. 1 [doi]
- Off-shore outsource DFT vs. build off-shore branch officesYu Huang 0005. 1 [doi]
- Correct by construction is guaranteed to failStephen K. Sunter. 1 [doi]
- Position statement: "have we overcome the challenges associated with SoC and multi-core testing?"Tim Wood. 1 [doi]
- How are we going to test SoC's on a PCB?Peter Collins. 1 [doi]
- Business constraints drive test decisionsFidel Muradali. 1 [doi]
- Partnering with customer to achieve high yieldJ. Wang. 1 [doi]
- Panel synopsis: reducing high-speed/RF test cost: guaranteed by design or guaranteed to fail?Hosam Haggag, Abhijit Chatterjee. 1 [doi]
- The case for outsourcing DFTJeffrey L. Roehr. 1 [doi]
- How are we going to test SoCs on a board?: the users viewpointGunnar Carlsson. 1 [doi]
- Business constraints drive test decisions - not vice versaSanjiv Taneja. 1 [doi]
- Test the test experts: do we know what we are doing?Rohit Kapur. 1 [doi]
- The final D-frontier: should DFT be outsourced?Luis Basto. 1 [doi]
- The ITC test compression shootoutScott Davidson. 1 [doi]
- Is the concern for soft-error overblown?Rajesh Raina. 1 [doi]
- Is the concern for soft-error overblown?Rajesh Raina. 2 [doi]
- Achieving higher yield through diagnosis?Srikanth Venkataraman. 2 [doi]
- Test compression - real issues and matching solutionsJanusz Rajski. 2 [doi]
- Have we overcome the challenges associated with SoC and multi-core testing?Rajesh Raina. 2 [doi]
- Business constraints drive test decisions planning, partnerships and successMichael Campbell. 2 [doi]
- Board and system test with SoC DFTGordon D. Robinson. 2 [doi]
- Outsourcing DFT: it can be done but it isn't easyLeRoy Winemberg. 2 [doi]
- Methods for improving test compressionNur A. Touba. 2 [doi]
- Panel discussion for "have we overcome the challenges associated with SoC and multi-core testing?"Nathan Chelstrom. 2 [doi]
- Panel: business constraints drive test decisionsJeff Schneider. 2 [doi]
- XMAX: a practical and efficient compression architectureKee Sup Kim. 2 [doi]
- Soft errors: is the concern for soft-errors overblown?Narayanan Vijaykrishnan. 2 [doi]
- Darwin, thy name is systemCraig Force. 2 [doi]
- Today's SOC test challengesYervant Zorian. 2 [doi]
- Test compression and logic BIST at your fingertipsShianling Wu, Laung-Terng Wang, Jin Woo Cho, Zhigang Jiang, Boryau Sheu. 2 [doi]
- Have we overcome the challenges associated with SoC and multi-core testing?Rajesh Raina. 2 [doi]
- The concern for soft errors is not overblownPia N. Sanda. 2 [doi]
- Encounter test OPMISR/sup +/ on-chip compressionBrion Keller. 2 [doi]
- Achieving higher yield through diagnosis-the ASIC perspectiveChris Schuermyer. 2 [doi]
- Outsourcing DFT: the right mixCarl Holzwarth. 2 [doi]
- Lowering the cost of test with a scalable ATE custom processor and timing IC containing 400 high-linearity timing verniersBrian Arkin. 6 [doi]
- STIL persistence [data reduction]Greg Maston, Julie Villar. 6 [doi]
- Noncontact wafer probe using wireless probe cardsChris Sellathamby, Md. Mahbub Reja, Lin Fu, Brenda Bai, Edwin Walter Reid, Steven Slupsky, Igor M. Filanovsky, Kris Iniewski. 6 [doi]
- Case study: effectiveness of high-speed scan based feed forward voltage testing in reducing DPPM on a high volume ASICJoel Lurkins, D. Hill, Brady Benware. 7 [doi]
- Gate exhaustive testingKyoung Youn Cho, Subhasish Mitra, Edward J. McCluskey. 7 [doi]
- Safely backdriving low voltage devices at in-circuit testChris Jacobsen, Tony Saye, Tom Trader. 7 [doi]
- The PXI carrier: a novel approach to ATE instrument developmentEric Kushnick. 7 [doi]
- Analyzing second-order effects between optimizations for system-level test-based model generationTiziana Margaria, Harald Raffelt, Bernhard Steffen. 7 [doi]
- Effect of lead free solders on in-circuit test processRosa D. Reinosa. 7 [doi]
- A practical perspective on reducing ASIC NTFsZoe Conroy, Geoff Richmond, Xinli Gu, Bill Eklow. 7 [doi]
- A self-timed structural test methodology for timing anomalies due to defects and process variationsAdit D. Singh. 7 [doi]
- Technique to improve the performance of time-interleaved A-D convertersKoji Asami. 7 [doi]
- Optimized reasoning-based diagnosis for non-random, board-level, production defectsCarlos O'Farrill, Merouane Moakil-Chbany, Bill Eklow. 7 [doi]
- Diagnosis and analysis of an analog circuit failure using time resolved emission microscopyAhmed Syed, Richard F. Herlein, Ben Cain, Frank Sauk. 7 [doi]
- Low cost multisite testing of quadruple band GSM transceiversLarry Zhang, Dale Heaton, Hank Largey. 7 [doi]
- An update on IEEE 1149.6 - successes and issuesBill Eklow. 7 [doi]
- A concurrent BIST scheme for on-line/off-line testing based on a pre-computed test setIoannis Voyiatzis, Dimitris Gizopoulos, Antonis M. Paschalis, Constantin Halatsis. 8 [doi]
- Cost-effective designs of field service for electronic systemsYu-Ting Lin, David Williams, Tony Ambler. 8 [doi]
- Calibrating clock stretch during AC scan testingJeff Rearick, Richard Rodgers. 8 [doi]
- A structured approach for the systematic test of embedded automotive communication systemsEric Armengaud, Florian Rothensteiner, Andreas Steininger, Roman Pallierer, Martin Horauer, Martin Zauner. 8 [doi]
- Compressed pattern diagnosis for scan chain failuresYu Huang 0005, Wu-Tung Cheng, Janusz Rajski. 8 [doi]
- A transparent solution for providing remote wired or wireless communication to board and system level boundary-scan architecturesPeter Collins, Ilka Reis, Mikko Simonen, Marc van Houcke. 8 [doi]
- IJTAG (internal JTAG): a step toward a DFT standardJeff Rearick, Bill Eklow, Ken Posse, Al Crouch, Ben Bennetts. 8 [doi]
- "Driver on a floppy" delivery of ATE instrumentation softwareDan Proskauer. 8 [doi]
- Synthesis of nonintrusive concurrent error detection using an even error detecting functionAvijit Dutta, Nur A. Touba. 8 [doi]
- Diagnosis framework for locating failed segments of path delay faultsYing-Yen Chen, Min-Pin Kuo, Jing-Jia Liou. 8 [doi]
- A novel process and hardware architecture to reduce burn-in costChris Schroeder, Jin Pan, Todd Albertson. 8 [doi]
- Testing high-speed, large scale implementation of SerDes I/Os on chips used in throughput computing systemsIain Robertson, Graham Hetherington, Tom Leslie, Ishwar Parulkar, Ronald Lesnikoski. 8 [doi]
- UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reductionLaung-Terng Wang, Khader S. Abdel-Hafez, Xiaoqing Wen, Boryau Sheu, Shianling Wu, Shyh-Horng Lin, Ming-Tung Chang. 8 [doi]
- Testing priority address encoder faults of content addressable memoriesJin-Fu Li. 8 [doi]
- Development of a software framework for open architecture ATEWilliam Fritzsche. 8 [doi]
- A comprehensive production test solution for 1.5Gb/s and 3Gb/s serial-ATA - based on AWG and undersampling techniquesYi Cai, Amit Bhattacharyya, Joe Martone, Anant Verma, William Burchanowski. 8 [doi]
- Power-scan chain: design for analog testabilityAmir Zjajo, Hendrik J. Bergveld, Rodger Schuttert, José Pineda de Gyvez. 8 [doi]
- Verifying flying prober performance - fitness is survivalBob Russell. 8 [doi]
- Drive only at speed functional testing; one of the techniques Intel is using to control test costsMike Tripp, Silvio Picano, Baruch Schnarch. 8 [doi]
- Test time reduction of successive approximation register A/D converter by selective code measurementShalabh Goyal, Abhijit Chatterjee, Mike Atia, Howard Iglehart, Chung Yu Chen, Bassem Shenouda, Nash Khouzam, Hosam Haggag. 8 [doi]
- The effects of defects on high-speed boardsKenneth P. Parker. 8 [doi]
- Test implications of lead-free implementation in a high-volume manufacturing environmentShu Peng, Sam Wong. 8 [doi]
- Test connections - tying application to processJohn M. Carulli Jr., Thomas J. Anderson. 8 [doi]
- Layering of the STIL extensionsGregory A. Maston, Tony Taylor. 8 [doi]
- Analysis of pseudo-interleaving AWGHideo Okawara. 8 [doi]
- March AB, March AB1: new March tests for unlinked dynamic memory faultsAlfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto. 8 [doi]
- Towards achieving relentless reliability gains in a server marketplace of teraflops, laptops, kilowatts, and "cost, cost, cost"...: making peace between a black art and the bottom lineJody Van Horn. 8 [doi]
- Forming N-detection test sets from one-detection test sets without test generationIrith Pomeranz, Sudhakar M. Reddy. 9 [doi]
- Invisible delay quality - SDQM model lights up what could not be seenYasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Yasuyuki Nozuyama, Seiji Kajihara. 9 [doi]
- Hierarchical DFT with enhancements for AC scan, test scheduling and on-chip compression - a case studyJeff Remmers, Darin Lee, Richard Fisette. 9 [doi]
- Testing throughput computing interconnect topologies with Tbits/sec bandwidth in manufacturing and in fieldIshwar Parulkar, Dawei Huang, Leandro Chua Jr., Drew Doblar. 9 [doi]
- Testability features of the first-generation CELL processorMack W. Riley, Louis B. Bushard, Nathan Paul Chelstrom, Naoki Kiryu, Steven Ross Ferguson. 9 [doi]
- A novel test methodology based on error-rate to support error-toleranceKuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer. 9 [doi]
- Functional vs. multi-VDD testing of RF circuitsEstella Silva, José Pineda de Gyvez, Guido Gronthoud. 9 [doi]
- Reducing test cost through the use of digital testers for analog testsJohn Sweeney, Alan Tsefrekas. 9 [doi]
- Evaluating ATE-equipment for volume diagnosisRalf Arnold, Andreas Leininger. 9 [doi]
- A scalable test strategy for network-on-chip routersAlexandre M. Amory, Eduardo Wenzel BriĂ£o, Érika F. Cota, Marcelo Lubaszewski, Fernando Gehm Moraes. 9 [doi]
- A test case for 3Gbps serial attached SCSI (SAS)Yi Cai, Liming Fang, Robert Ratemo, J. Liu, K. Gross, Michael Kozma. 9 [doi]
- Simulation of transients caused by single-event upsets in combinational logicKartik Mohanram. 9 [doi]
- A random access scans architecture to reduce hardware overheadAnand S. Mudlapur, Vishwani D. Agrawal, Adit D. Singh. 9 [doi]
- Node sensitivity analysis for soft errors in CMOS logicBalkaran S. Gill, Christos A. Papachristou, Francis G. Wolff, Norbert Seifert. 9 [doi]
- Parallel, multi-DUT testing in an open architecture test systemToshiaki Adachi, Ankan K. Pramanick, Mark Elston. 9 [doi]
- Defect-based RF testing using a new catastrophic fault modelErkan Acar, Sule Ozev. 9 [doi]
- X-filter: filtering unknowns from compacted test responsesManish Sharma, Wu-Tung Cheng. 9 [doi]
- Chasing subtle embedded RAM defects for nanometer technologiesTheo J. Powell, Amrendra Kumar, Joseph Rayhawk, Nilanjan Mukherjee. 9 [doi]
- Test methodology for Freescale's high performance e600 core based on PowerPC/spl reg/ instruction set architectureNandu Tendolkar, Dawit Belete, Ashutosh Razdan, Hereman Reyes, Bill Schwarz, Marie Sullivan. 9 [doi]
- A novel stuck-at based method for transistor stuck-open fault diagnosisXinyue Fan, Will R. Moore, Camelia Hora, Guido Gronthoud. 9 [doi]
- Multiple tests for each gate delay fault: higher coverage and lower test application costShahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer. 9 [doi]
- Column parity and row selection (CPRS): a BIST diagnosis technique for multiple errors in multiple scan chainsHung-Mao Lin, James Chien-Mo Li. 9 [doi]
- Bead probes in practiceKenneth P. Parker. 9 [doi]
- Reconfigurable systems self-healing using mobile hardware agentsAlfredo Benso, Alessandro Cilardo, Nicola Mazzocca, Liviu Miclea, Paolo Prinetto, SzilĂ¡rd Enyedi. 9 [doi]
- Identification of systematic yield limiters in complex ASICS through volume structural test fail data visualization and analysisChris Schuermyer, Kevin Cota, Robert Madge, Brady Benware. 9 [doi]
- Enabling yield analysis with X-compactZoran Stanojevic, Ruifeng Guo, Subhasish Mitra, Srikanth Venkataraman. 9 [doi]
- Full-speed field-programmable memory BIST architectureXiaogang Du, Nilanjan Mukherjee, Wu-Tung Cheng, Sudhakar M. Reddy. 9 [doi]
- Impact of back side circuit edit on active device performance in bulk silicon ICsUwe Kerst, Rudolf Schlangen, A. Kabakow, Erwan Le Roy, Ted Lundquist, Siegfried Pauthner. 9 [doi]
- High speed differential pin electronics over 6.4 GbpsAtsushi Oshima, Toshihiro Nomura. 9 [doi]
- Use of MISRs for compression and diagnosticsBrion L. Keller, Thomas Bartenstein. 9 [doi]
- A low power and low cost scan test architecture for multi-clock domain SoCs using virtual divide and conquerArasu T. Senthil, C. P. Ravikumar, Soumitra Kumar Nandy. 9 [doi]
- An optimal test pattern selection method to improve the defect coverageYuxin Tian, Michael R. Grimaila, Weiping Shi, M. Ray Mercer. 9 [doi]
- CMOS high-speed, high-precision timing generator for 4.266-Gbps memory test systemMasakatsu Suda, Kazuhiro Yamamoto, Toshiyuki Okayasu, Shusuke Kantake, Satoshi Sudou, Daisuke Watanabe. 9 [doi]
- Variance reduction and outliers: statistical analysis of semiconductor test dataW. Robert Daasch, Robert Madge. 9 [doi]
- An advanced optical diagnostic technique of IBM z990 eServer microprocessorPeilin Song, Franco Stellari, Bill Huott, Otto Wagner, Uma Srinivasan, Yuen H. Chan, Rick Rizzolo, H. J. Nam, James P. Eckhardt, Timothy G. McNamara, Ching-Lung Tong, Alan J. Weger, Moyra K. McManus. 9 [doi]
- Word line pulsing technique for stability fault detection in SRAM cellsAndrei Pavlov, Mohamed Azimane, José Pineda de Gyvez, Manoj Sachdev. 10 [doi]
- Remote boundary-scan system test control for the ATCA standardDavid Bäckström, Gunnar Carlsson, Erik Larsson. 10 [doi]
- Computational intelligence based testing for semiconductor measurement systemsEric Liau, Doris Schmitt-Landsiedel. 10 [doi]
- A static noise impact analysis methodology for evaluating transient error effects in digital VLSI circuitsChong Zhao, Xiaoliang Bai, Sujit Dey. 10 [doi]
- High-performance ADC linearity test using low-precision signals in non-stationary environmentsLe Jin, Kumar L. Parthasarathy, Turker Kuyel, Randall L. Geiger, Degang Chen. 10 [doi]
- I/sub DDQ/ test using built-in current sensing of supply line voltage dropBin Xue, D. M. H. Walker. 10 [doi]
- The value of statistical testing for quality, yield and test cost improvementRobert Madge, Brady Benware, Mark Ward, W. Robert Daasch. 10 [doi]
- Hazard-aware statistical timing simulation and its applications in screening frequency-dependent defectsBenjamin N. Lee, Hui Li, Li-C. Wang, Magdy S. Abadir. 10 [doi]
- Using built-in self-test and adaptive recovery for defect tolerance in molecular electronics-based nanofabricsZhanglei Wang, Krishnendu Chakrabarty. 10 [doi]
- Data-driven models for statistical testing: measurements, estimates and residualsW. Robert Daasch, Robert Madge. 10 [doi]
- Jitter spectrum analysis using continuous time interval analyzer (CTIA)Sassan Tabatabaei, Freddy Ben-Zeev, Touraj Farahmand. 10 [doi]
- JTAG-based vector and chain management for system testBradford G. Van Treuren, Bryan E. Peterson, José M. Miranda. 10 [doi]
- Progressive random access scan: a simultaneous solution to test power, test data volume and test timeDong Hyun Baik, Kewal K. Saluja. 10 [doi]
- External memory BIST for system-in-packageKaname Yamasaki, Iwao Suzuki, Azumi Kobayashi, Keiichi Horie, Yasuharu Kobayashi, Hideyuki Aoki, Hideki Hayashi, Kenichi Tada, Koki Tsutsumida, Keiichi Higeta. 10 [doi]
- Programmable memory BISTSlimane Boutobza, Michael Nicolaidis, Kheiredine M. Lamara, Andrea Costa. 10 [doi]
- Test data compression for IP embedded cores using selective encoding of scan slicesZhanglei Wang, Krishnendu Chakrabarty. 10 [doi]
- Methods for improving transition delay fault coverage using broadside testsNarendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz. 10 [doi]
- A vector-based approach for power supply noise analysis in test compactionJing Wang, Ziding Yue, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker. 10 [doi]
- Structural tests for jitter tolerance in SerDes receiversStephen K. Sunter, Aubin Roy. 10 [doi]
- Test and debug features of the RTO7 chipKees van Kaam, Bart Vermeulen, Henk Jan Bergveld. 10 [doi]
- Efficient compression of deterministic patterns into multiple PRPG seedsPeter Wohl, John A. Waicukauski, Sanjay Patel, Francisco DaSilva, Thomas W. Williams, Rohit Kapur. 10 [doi]
- Logic proximity bridgesEric N. Tran, Vamsee Krishna, Sujit T. Zachariah, Sreejit Chakravarty. 10 [doi]
- Efficient SAT-based combinational ATPG using multi-level don't-caresNikhil Saluja, Sunil P. Khatri. 10 [doi]
- A DDJ calibration methodology for high-speed test and measurement equipmentsTouraj Farahmand, Sassan Tabatabaei, Freddy Ben-Zeev, André Ivanov. 10 [doi]
- XWRC: externally-loaded weighted random pattern testing for input test data compressionSeongmoon Wang, Kedarnath J. Balakrishnan, Srimat T. Chakradhar. 10 [doi]
- A new approach for massive parallel scan designWoo Cheol Chung, Dong Sam Ha. 10 [doi]
- A new probing technique for high-speed/high-density printed circuit boardsKenneth P. Parker. 10 [doi]
- Understanding NTF components from the fieldScott Davidson. 10 [doi]
- A test point selection method for data converters using Rademacher functions and wavelet transformsChandra Carter, Simon S. Ang. 10 [doi]
- Definitions of jitter measurement terms and relationshipsIliya Zamek, Steve Zamek. 10 [doi]
- Diagnosis with convolutional compactors in presence of unknown statesGrzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer. 10 [doi]
- Compression mode diagnosis enables high volume monitoring diagnosis flowAndreas Leininger, Peter Muhmenthaler, Wu-Tung Cheng, Nagesh Tamarapalli, Wu Yang, Hans Tsai. 10 [doi]
- Production test enhancement techniques for MB-OFDM ultra-wide band (UWB) devices: EVM and CCDFSoumendu Bhattacharya, Rajarajan Senguttuvan, Abhijit Chatterjee. 10 [doi]
- Test generation for ultra-high-speed asynchronous pipelinesFeng Shi, Yiorgos Makris, Steven M. Nowick, Montek Singh. 10 [doi]
- Logic soft errors: a major barrier to robust platform designSubhasish Mitra, Ming Zhang, T. M. Mak, Norbert Seifert, Victor Zia, Kee Sup Kim. 10 [doi]
- Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoringSaibal Mukhopadhyay, Kunhyuk Kang, Hamid Mahmoodi, Kaushik Roy. 10 [doi]
- Transient fault characterization in dynamic noisy environmentsIlia Polian, John P. Hayes, Sandip Kundu, Bernd Becker. 10 [doi]
- On concurrent test of wrapped cores and unwrapped logic blocks in SOCsQiang Xu, Nicola Nicolici. 10 [doi]
- Jitter transformations in measurement instruments and discrepancies between measurement resultsIliya Zamek, Steve Zamek. 10 [doi]
- Definition of a robust modular SOC test architecture; resurrection of the single TAM daisy-chainTom Waayers, Richard Morren, Roberto Grandi. 10 [doi]
- Simulation-based target test generation techniques for improving the robustness of a software-based-self-test methodologyCharles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng, Wei-Ting Liu, Ji-Jan Chen. 10 [doi]
- Testing and debugging delay faults in dynamic circuitsRamyanshu Datta, Sani R. Nassif, Robert K. Montoye, Jacob A. Abraham. 10 [doi]
- Low-capture-power test generation for scan-based at-speed testingXiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita. 10 [doi]
- A methodology for testing one-hot transmission gate multiplexersTeresa L. McLaurin, Frank Frederick, Rich Slobodnik. 10 [doi]
- A leakage control system for thermal stability during burn-in testMesut Meterelliyoz, Hamid Mahmoodi, Kaushik Roy. 10 [doi]
- A 16-bit resistor string DAC with full-calibration at final testKumar L. Parthasarathy, Turker Kuyel, Zhongjun Yu, Degang Chen, Randall L. Geiger. 10 [doi]
- Microprocessor silicon debug based on failure propagation tracingOlivier Caty, Peter Dahlgren, Ismet Bayraktaroglu. 10 [doi]
- Comparative study of CA with phase shifters and GLFSRsS. Chidambaram, Dimitrios Kagaris, Dhiraj K. Pradhan. 10 [doi]
- IEEE 1500 utilization in SOC design and testYervant Zorian, Avetik Yessayan. 10 [doi]
- Power-supply noise in SoCs: ATPG, estimation and controlMehrdad Nourani, Arun Radhakrishnan. 10 [doi]
- A strategy for board level in-system programmable built-in assisted test and built-in self testJoshua Ferry, Jozef Scesnak, Shoeib Shaikh. 10 [doi]
- Design and analysis of multiple weight linear compactors of responses containing unknown valuesThomas Clouqueur, Kamran Zarrineh, Kewal K. Saluja, Hideo Fujiwara. 10 [doi]
- Built-in constraint resolutionGrady Giles, Joel Irby, Daniela Toneva, Kun-Han Tsai. 10 [doi]
- Defect-oriented testing and diagnosis of digital microfluidics-based biochipsFei Su, William L. Hwang, Arindam Mukherjee, Krishnendu Chakrabarty. 10 [doi]
- Burn-in reduction using principal component analysisAmit Nahar, W. Robert Daasch, S. Subramaniam. 10 [doi]
- Analysis of error-masking and X-masking probabilities for convolutional compactorsMasayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki. 10 [doi]
- Automated mapping of pre-computed module-level test sequences to processor instructionsS. Guramurthy, Shobha Vasudevan, Jacob A. Abraham. 10 [doi]
- Enhanced launch-off-capture transition fault testingNisar Ahmed, Mohammad Tehranipoor, C. P. Ravikumar. 10 [doi]
- Production-oriented interface testing for PCI-Express by enhanced loop-back techniqueMitchell Lin, Kwang-Ting Cheng, Jimmy Hsu, M.-C. Sun, Jason Chen, Shelton Lu. 10 [doi]
- A wideband low-noise ATE-based method for measuring jitter in GHz signalsTakahiro J. Yamaguchi, Masahiro Ishida, Mani Soma. 10 [doi]
- Third-Order Phase Lock Loop Measurement and CharacterizationJ. Ma, M. Li, M. Marlett. 56-65 [doi]
- How are we going to test socs on a board? the users viewpointGunnar Carlsson. 1263 [doi]
- Is the concern for soft-error overblown?Rajesh Galivanche. 1269 [doi]