Narendra Devta-Prasanna - researchr alias

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Viewing Publication 1 - 24 from 24

2014

Small-Delay Defect Coverage MetricsNarendra Devta-Prasanna, Sandeep Kumar Goel. In Sandeep Kumar Goel, Krishnendu Chakrabarty, editors, Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits. pages 185-210, CRC Press, 2014.

Hybrid/Top-off Test Pattern Generation Schemes for Small-Delay DefectsSandeep Kumar Goel, Narendra Devta-Prasanna. In Sandeep Kumar Goel, Krishnendu Chakrabarty, editors, Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits. pages 147-160, CRC Press, 2014.

2012

2010

Clock Gate Test PointsNarendra Devta-Prasanna, Arun Gunda. itc 2010: 84-93 [doi]

Multiple fault activation cycle tests for transistor stuck-open faultsNarendra Devta-Prasanna, Arun Gunda, Sudhakar M. Reddy, Irith Pomeranz. itc 2010: 821 [doi]

2009

Accurate measurement of small delay defect coverage of test patternsNarendra Devta-Prasanna, Sandeep Kumar Goel, Arun Gunda, Mark Ward, P. Krishnamurthy. itc 2009: 1-10 [doi]

Comparing the effectiveness of deterministic bridge fault and multiple-detect stuck fault patterns for physical bridge defects: A simulation and silicon studySandeep Kumar Goel, Narendra Devta-Prasanna, Mark Ward. itc 2009: 1-10 [doi]

Effective and Efficient Test Pattern Generation for Small Delay DefectSandeep Kumar Goel, Narendra Devta-Prasanna, Ritesh P. Turakhia. vts 2009: 111-116 [doi]

Detectability of internal bridging faults in scan chainsFan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz. aspdac 2009: 678-683 [doi]

Improving the Detectability of Resistive Open Faults in Scan CellsFan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz. dft 2009: 383-391 [doi]

2008

Comparative study of centralised and distributed compatibility-based test data compressionAhmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda. iet-cdt, 2(2):108-117, 2008. [doi]

Detection of Internal Stuck-open Faults in Scan ChainsFan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz. itc 2008: 1-10 [doi]

An Enhanced Logic BIST Architecture for Online TestingFan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz. iolts 2008: 10-15 [doi]

Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan CellsFan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz. dft 2008: 394-402 [doi]

On the Detectability of Scan Chain Internal Faults  An Industrial Case StudyFan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz. vts 2008: 79-84 [doi]

2007

Scan Test Cost and Power Reduction Through Systematic Scan ReconfigurationAhmad A. Al-Yamani, Narendra Devta-Prasanna, Erik Chmelar, M. Grinchuk, Arun Gunda. tcad, 26(5):907-918, 2007. [doi]

Systematic Scan ReconfigurationAhmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda. aspdac 2007: 738-743 [doi]

2006

Test Generation for Open Defects in CMOS CircuitsNarendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz. dft 2006: 41-49 [doi]

A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay FaultsNarendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz. emnets 2006: 185-192 [doi]

2005

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