Table of Contents

• Automated synthesis and verification of embedded systems: wishful thinking or reality?Wolfgang Rosenstiel. [doi]
• From restrictive to prescriptive designLeon Stok. [doi]
• Challenges to EDA system from the view point of processor design and technology driversMitsuo Saito. [doi]
• Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architecturesAvinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri, Janet Meiling Wang. 1-6 [doi]
• Analysis of communication delay bounds for network on chipsYue Qian, Zhonghai Lu, Wenhua Dou. 7-12 [doi]
• Frequent value compression in packet-based NoC architecturesPing Zhou, Bo Zhao, Yu Du, Yi Xu, Youtao Zhang, Jun Yang, Li Zhao. 13-18 [doi]
• Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architectureYu-Ju Hong, Ya-Shih Huang, Juinn-Dar Huang. 19-24 [doi]
• Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applicationsSudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi. 25-30 [doi]
• Stochastic thermal simulation considering spatial correlated within-die process variationsPei-Yu Huang, Jia-Hong Wu, Yu-Min Lee. 31-36 [doi]
• A control theory approach for thermal balancing of MPSoCFrancesco Zanini, David Atienza, Giovanni De Micheli. 37-42 [doi]
• Thermal optimization in multi-granularity multi-core floorplanningMichael B. Healy, Hsien-Hsin S. Lee, Gabriel H. Loh, Sung Kyu Lim. 43-48 [doi]
• Temperature-aware dynamic frequency and voltage scaling for reliability and yield enhancementYu-Wei Yang, Katherine Shu-Min Li. 49-54 [doi]
• A multiple supply voltage based power reduction method in 3-D ICs considering process variations and thermal effectsShih-An Yu, Pei-Yu Huang, Yu-Min Lee. 55-60 [doi]
• FastYield: variation-aware, layout-driven simultaneous binding and module selection for performance yield optimizationGregory Lucas, Scott Cromar, Deming Chen. 61-66 [doi]
• CriAS: a performance-driven criticality-aware synthesis flow for on-chip multicycle communication architectureChia-I Chen, Juinn-Dar Huang. 67-72 [doi]
• Tolerating process variations in high-level synthesis using transparent latchesYibo Chen, Yuan Xie. 73-78 [doi]
• Variation-aware resource sharing and binding in behavioral synthesisFeng Wang 0004, Yuan Xie, Andres Takach. 79-84 [doi]
• Peak temperature control in thermal-aware behavioral synthesis through allocating the number of resourcesJunbo Yu, Qiang Zhou, Jinian Bian. 85-90 [doi]
• A wireless real-time on-chip bus trace systemShusuke Kawai, Takayuki Ikari, Yutaka Takikawa, Hiroki Ishikuro, Tadahiro Kuroda. 91-92 [doi]
• CKVdd: a self-stabilization ramp-vdd technique for dynamic power reductionChin-Hsien Wang, Ching-Hwa Cheng, Jiun-In Guo. 93-94 [doi]
• A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETsKen Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya. 95-96 [doi]
• A 100Mbps, 0.19mW asynchronous threshold detector with DC power-free pulse discrimination for impulse UWB receiverLechang Liu, Yoshio Miyamoto, Zhiwei Zhou, Kosuke Sakaida, Jisun Ryu, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai. 97-98 [doi]
• Low-power CMOS transceiver circuits for 60GHz band millimeter-wave impulse radioAhmet Oncu, Minoru Fujishima. 99-100 [doi]
• An inductor-less MPPT design for light energy harvesting systemsHui Shao, Chi-Ying Tsui, Wing-Hung Ki. 101-102 [doi]
• A 1 GHz CMOS comparator with dynamic offset control techniqueXiaolei Zhu, Sanroku Tsukamoto, Tadahiro Kuroda. 103-104 [doi]
• Circuit design using stripe-shaped PMELA TFTs on glassKeita Ikai, Jinmyoung Kim, Makoto Ikeda, Kunihiro Asada. 105-106 [doi]
• Low energy level converter design for sub-V::th:: logicsHui Shao, Chi-Ying Tsui. 107-108 [doi]
• A Time-to-Digital Converter with small circuitryKazuya Shimizu, Masato Kaneta, HaiJun Lin, Haruo Kobayashi, Nobukazu Takai, Masao Hotta. 109-110 [doi]
• A V::DD:: independent temperature sensor circuit with scaled CMOS processH. Oshiyama, T. Matsuda, K. Suzuki, Hideyuki Iwata, Takashi Ohzone. 111-112 [doi]
• A current-mode DC-DC converter using a quadratic slope compensation schemeChihiro Kawabata, Yasuhiro Sugimoto. 113-114 [doi]
• Ultra low-power ANSI S1.11 filter bank for digital hearing aidsYu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li, Chou-Kun Lin, Chih-Wei Liu. 115-116 [doi]
• An 11, 424 gate-count dynamic optically reconfigurable gate array with a photodiode memory architectureDaisaku Seto, Minoru Watanabe. 117-118 [doi]
• A low-power FPGA based on autonomous fine-grain power-gatingShota Ishihara, Masanori Hariyama, Michitaka Kameyama. 119-120 [doi]
• A 52-mW 8.29mm:::2::: 19-mode LDPC decoder chip for mobile WiMAX applicationsXin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, An-Yeu Wu. 121-122 [doi]
• A full-synthesizable high-precision built-in delay time measurement circuitMing-Chien Tsai, Ching-Hwa Cheng. 123-124 [doi]
• A dynamic quality-scalable H.264 video encoder chipHsiu-Cheng Chang, Yao-Chang Yang, Jia-Wei Chen, Ching-Lung Su, Cheng-An Chien, Jiun-In Guo, Jinn-Shyan Wang. 125-126 [doi]
• A high performance LDPC decoder for IEEE802.11n standardWen Ji, Yuta Abe, Takeshi Ikenaga, Satoshi Goto. 127-128 [doi]
• Design and chip implementation of the ubiquitous processor HCgorillaMasa-Aki Fukase, Kazunori Noda, Atsuko Yokoyama, Tomoaki Sato. 129-130 [doi]
• An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronicsLiang-Bi Chen, Ruei-Ting Gu, Wei-Sheng Huang, Chien-Chou Wang, Wen-Chi Shiue, Tsung-Yu Ho, Yun-Nan Chang, Shen-Fu Hsiao, Chung-Nan Lee, Ing-Jer Huang. 131-132 [doi]
• A multi-task-oriented security processing architecture with powerful extensibilityDan Cao, Jun Han, Xiaoyang Zeng, Shi-ting Lu. 133-134 [doi]
• A delay-optimized universal FPGA routing architectureWu Fang, Zhang Huowen, Duan Lei, Lai Jinmei, Wang Yuan, Tong Jiarong. 135-136 [doi]
• Timing variation-aware task scheduling and binding for MPSoCHaNeul Chon, Taewhan Kim. 137-142 [doi]
• Flexible and abstract communication and interconnect modeling for MPSoCKatalin Popovici, Ahmed Amine Jerraya. 143-148 [doi]
• Partial order method for timed simulation of system-level MPSoC designsEric Cheung, Harry Hsieh, Felice Balarin. 149-154 [doi]
• A UML-based approach for heterogeneous IP integrationZhenxin Sun, Weng-Fai Wong. 155-160 [doi]
• Statistical modeling and analysis of chip-level leakage power by spectral stochastic methodRuijing Shen, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong. 161-166 [doi]
• On the futility of statistical power optimizationJason Cong, Puneet Gupta, John Lee. 167-172 [doi]
• Timing driven power gating in high-level synthesisShih-Hsu Huang, Chun-Hua Cheng. 173-178 [doi]
• Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitorsPingqiang Zhou, Karthikk Sridharan, Sachin S. Sapatnekar. 179-184 [doi]
• Incremental and on-demand random walk for iterative power distribution network analysisYiyu Shi, Wei Yao, Jinjun Xiong, Lei He. 185-190 [doi]
• SAT-controlled redundancy addition and removal: a novel circuit restructuring techniqueChi-An Wu, Ting-Hao Lin, Shao-Lun Huang, Chung-Yang Huang. 191-196 [doi]
• On improved scheme for digital circuit rewiring and application on further improving FPGA technology mappingF. S. Chim, T. K. Lam, Y. L. Wu. 197-202 [doi]
• Hybrid LZA: a near optimal implementation of the leading zero anticipatorAmit Verma, Ajay K. Verma, Philip Brisk, Paolo Ienne. 203-209 [doi]
• An optimized design for serial-parallel finite field multiplication over ::::GF::::(2:::::::m:::::::) based on all-one polynomialsP. K. Meher, Yajun Ha, Chiou-Yng Lee. 210-215 [doi]
• Aspects of GPU for general purpose high performance computingReiji Suda, Takayuki Aoki, Shoichi Hirasawa, Akira Nukada, Hiroki Honda, Satoshi Matsuoka. 216-223 [doi]
• Designing and optimizing compute kernels on NVIDIA GPUsDamir A. Jamsek. 224-229 [doi]
• Parallelizing fundamental algorithms such as sorting on multi-core processors for EDA accelerationMasato Edahiro. 230-233 [doi]
• System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs)Xiangyu Dong, Yuan Xie. 234-241 [doi]
• Synthesis of networks on chips for 3D systems on chipsSrinivasan Murali, Ciprian Seiculescu, Luca Benini, Giovanni De Micheli. 242-247 [doi]
• An application-centered design flow for self reconfigurable systems implementationFabio Cancare, Marco D. Santambrogio, Donatella Sciuto. 248-253 [doi]
• System-level process variability compensation on memory organizations: on the scalability of multi-mode memoriesConcepción Sanz, Manuel Prieto, José Ignacio Gómez, Antonis Papanikolaou, Francky Catthoor. 254-259 [doi]
• Accelerating statistical static timing analysis using graphics processing unitsKanupriya Gulati, Sunil P. Khatri. 260-265 [doi]
• Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error predictionHiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye. 266-271 [doi]
• Statistical analysis of on-chip power grid networks by variational extended truncated balanced realization methodDuo Li, Sheldon X.-D. Tan, Gengsheng Chen, Xuan Zeng. 272-277 [doi]
• Bound-based identification of timing-violating paths under variabilityLin Xie, Azadeh Davoodi. 278-283 [doi]
• Adaptive techniques for overcoming performance degradation due to aging in digital circuitsSanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar. 284-289 [doi]
• Introduction to hardware-dependent software design hardware-dependent software for multi- and many-core embedded systemsRainer Dömer, Andreas Gerstlauer, Wolfgang Müller 0003. 290-292 [doi]
• Using a dataflow abstracted virtual prototype for HdS-designWolfgang Ecker, Stefan Heinen, Michael Velten. 293-300 [doi]
• Needs and trends in embedded software development for consumer electronicsYasutaka Tsunakawa. 301-303 [doi]
• Hardware-dependent software synthesis for many-core embedded systemsSamar Abdi, Gunar Schirner, Ines Viskic, Hansu Cho, Yonghyun Hwang, Lochi Lo Chi Yu Lo, Daniel Gajski. 304-310 [doi]
• Computation and data transfer co-scheduling for interconnection bus minimizationCathy Qun Xu, Chun Jason Xue, Bessie C. Hu, Edwin Hsing-Mean Sha. 311-316 [doi]
• Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platformAntonino Tumeo, Marco Branca, Lorenzo Camerini, Marco Ceriani, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto. 317-322 [doi]
• Variability-aware robust design space exploration of chip multiprocessor architecturesGianluca Palermo, Cristina Silvano, Vittorio Zaccaria. 323-328 [doi]
• Partial conflict-relieving programmable address shuffler for parallel memories in multi-core processorYoung-Su Kwon, Bontae Koo, Nak-Woong Eum. 329-334 [doi]
• HitME: low power Hit MEmory buffer for embedded systemsAndhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatovic. 335-340 [doi]
• Signal skew aware floorplanning and bumper signal assignment technique for flip-chipCheng-Yu Wang, Wai-Kei Mak. 341-346 [doi]
• A novel thermal optimization flow using incremental floorplanning for 3D ICsXin Li, Yuchun Ma, Xianlong Hong. 347-352 [doi]
• Analog placement with common centroid and 1-D symmetry constraintsLinfu Xiao, Evangeline F. Y. Young. 353-360 [doi]
• A multilevel analytical placement for 3D ICsJason Cong, Guojie Luo. 361-366 [doi]
• Exploring adjacency in floorplanningJia Wang, Hai Zhou. 367-372 [doi]
• Stochastic current prediction enabled frequency actuator for runtime resonance noise reductionYiyu Shi, Jinjun Xiong, Howard Chen, Lei He. 373-378 [doi]
• Fast analysis of nontree-clock network considering environmental uncertainty by parameterized and incremental macromodelingHai Wang, Hao Yu, Sheldon X.-D. Tan. 379-384 [doi]
• High performance on-chip differential signaling using passive compensation for global communicationLing Zhang, Yulei Zhang, Akira Tsuchiya, Masanori Hashimoto, Ernest S. Kuh, Chung-Kuan Cheng. 385-390 [doi]
• Noise minimization during power-up stage for a multi-domain power networkWanping Zhang, Yi Zhu, Wenjian Yu, Amirali Shayan Arani, Renshen Wang, Zhi Zhu, Chung-Kuan Cheng. 391-396 [doi]
• Parallel transistor level circuit simulation using domain decomposition methodsHe Peng, Chung-Kuan Cheng. 397-402 [doi]
• Fast circuit simulation on graphics processing unitsKanupriya Gulati, John F. Croix, Sunil P. Khatri, Rahm Shastry. 403-408 [doi]
• Three-dimensional integration technology and integrated systemsMitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka. 409-415 [doi]
• A 3D prototyping chip based on a wafer-level stacking technologyNobuaki Miyakawa. 416-420 [doi]
• CAD challenges for 3D ICsDavid S. Kung, Ruchir Puri. 421-422 [doi]
• Addressing thermal and power delivery bottlenecks in 3D circuitsSachin S. Sapatnekar. 423-428 [doi]
• The road to 3D EDA tool readinessCharles Chiang, Subarna Sinha. 429-436 [doi]
• System-level exploration tool for energy-aware memory management in the design of multidimensional signal processing systemsFlorin Balasa, Ilie I. Luican, Hongwei Zhu, Doru V. Nasui. 443-448 [doi]
• Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processorsIttetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai. 449-454 [doi]
• A framework for estimating NBTI degradation of microarchitectural componentsMichael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan. 455-460 [doi]
• Efficient analytical determination of the SEU-induced pulse shapeRajesh Garg, Sunil P. Khatri. 461-467 [doi]
• Post-routing redundant via insertion with wire spreading capabilityCheok-Kei Lei, Po-Yi Chiang, Yu-Min Lee. 468-473 [doi]
• Accounting for non-linear dependence using function driven component analysisLerong Cheng, Puneet Gupta, Lei He. 474-479 [doi]
• Risk aversion min-period retiming under process variationsJia Wang, Hai Zhou. 480-485 [doi]
• Timing analysis and optimization implications of bimodal CD distribution in double patterning lithographyKwangok Jeong, Andrew B. Kahng. 486-491 [doi]
• Scheduled voltage scaling for increasing lifetime in the presence of NBTILide Zhang, Robert P. Dick. 492-497 [doi]
• Efficiently finding the best solution with multi-objectives from multiple topologies in topology library of analog circuitYu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya. 498-503 [doi]
• Automated design and optimization of circuits in emerging technologiesRajesh Amratlal Thakker, Chaitanya Sathe, Angada B. Sachid, Maryam Shojaei Baghini, V. Ramgopal Rao, Mahesh B. Patil. 504-509 [doi]
• An automated design approach for CMOS LDO regulatorsSamiran DasGupta, Pradip Mandal. 510-515 [doi]
• A SCORE macromodel for PLL designs to analyze supply noise interaction issues at behavioral levelChin-Cheng Kuo, Pei-Syun Lin, Chien-Nan Jimmy Liu. 516-521 [doi]
• Gen-Adler: the Generalized Adler s equation for injection locking analysis in oscillatorsPrateek Bhansali, Jaijeet S. Roychowdhury. 522-527 [doi]
• Development of full-HD multi-standard video CODEC IP based on heterogeneous multiprocessor architectureHiroaki Nakata, Koji Hosogi, Masakazu Ehama, Takafumi Yuasa, Toru Fujihira, Kenichi Iwata, Motoki Kimura, Fumitaka Izuhara, Seiji Mochizuki, Masaki Nobori. 528-534 [doi]
• A 65nm dual-mode baseband and multimedia application processor SoC with advanced power and memory managementTatsuya Kamei, Tetsuhiro Yamada, Takao Koike, Masayuki Ito, Takahiro Irita, Kenichi Nitta, Toshihiro Hattori, Shinichi Yoshioka. 535-539 [doi]
• UniPhier: series development and SoC managementYoshito Nishimichi, Nobuo Higaki, Masataka Osaka, Seiji Horii, Hisato Yoshida. 540-545 [doi]
• Automatic instrumentation of embedded software for high level hardware/software co-simulationAimen Bouchhima, Patrice Gerin, Frédéric Pétrot. 546-551 [doi]
• Fast and accurate performance simulation of embedded software for MPSoCEric Cheung, Harry Hsieh, Felice Balarin. 552-557 [doi]
• Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal modelChen Kang Lo, Ren-Song Tsay. 558-563 [doi]
• A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processorFarhad Mehdipour, Hamid Noori, Bahman Javadi, Hiroaki Honda, Koji Inoue, Kazuaki Murakami. 564-569 [doi]
• Efficient simulated evolution based rerouting and congestion-relaxed layer assignment on 3-D global routingKe-Ren Dai, Wen-Hao Liu, Yih-Lang Li. 570-575 [doi]
• FastRoute 4.0: global router with efficient via minimizationYue Xu, Yanheng Zhang, Chris Chu. 576-581 [doi]
• High-performance global routing with fast overflow reductionHuang-Yu Chen, Chin-Hsiung Hsu, Yao-Wen Chang. 582-587 [doi]
• IO connection assignment and RDL routing for flip-chip designsJin-Tai Yan, Zhi-Wei Chen. 588-593 [doi]
• On using SAT to ordered escape problemsLijuan Luo, Martin D. F. Wong. 594-599 [doi]
• A fast longer path algorithm for routing grid with obstacles using biconnectivity based length upper boundYukihide Kohira, Suguru Suehiro, Atsushi Takahashi. 600-605 [doi]
• Thermal-aware post compilation for VLIW architecturesWen-Wen Hsieh, TingTing Hwang. 606-611 [doi]
• A software solution for dynamic stack management on scratch pad memoryArun Kannan, Aviral Shrivastava, Amit Pabalkar, Jongeun Lee. 612-617 [doi]
• Compiler-managed register file protection for energy-efficient soft error reductionJongeun Lee, Aviral Shrivastava. 618-623 [doi]
• Code decomposition and recomposition for enhancing embedded software performanceYoungchul Cho, Kiyoung Choi. 624-629 [doi]
• Dependent latch identification in the reachable state spaceChen-Hsuan Lin, Chun-Yao Wang. 630-635 [doi]
• Complete-k-distinguishability for retiming and resynthesis equivalence checking without restricting synthesisNikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee. 636-641 [doi]
• Multi-clock SVA synthesis without re-writingJiang Long, Andrew Seawright, Paparao Kavalipati. 648-653 [doi]
• Automatic formal verification of clock domain crossing signalsBing Li, Chris Ka-Kei Kwok. 654-659 [doi]
• Fast false path identification based on functional unsensitizability using RTL informationYuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara. 660-665 [doi]
• Conflict driven scan chain configuration for high transition fault coverage and low test powerZhen Chen, Boxue Yin, Dong Xiang. 666-671 [doi]
• Dynamic test compaction for a random test generation procedure with input cube avoidanceIrith Pomeranz, Sudhakar M. Reddy. 672-677 [doi]
• Detectability of internal bridging faults in scan chainsFan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz. 678-683 [doi]
• Fault modeling and testing of retention flip-flops in low power designsBing-Chuan Bai, Augusli Kifli, Chien-Mo James Li, Kun-Cheng Wu. 684-689 [doi]
• Design methods for pipeline & delta-sigma A-to-D converters with convex optimizationKazuo Matsukawa, Takashi Morie, Yusuke Tokunaga, Shiro Sakiyama, Yosuke Mitani, Masao Takayama, Takuji Miki, Akinori Matsumoto, Koji Obata, Shiro Dosho. 690-695 [doi]
• A low-jitter 1.5-GHz and large-EMI reduction 10-dBm spread-spectrum clock generator for Serial-ATATakashi Kawamoto, Masaru Kokubo. 696-701 [doi]
• RF-analog circuit design in scaled SoCNobuyuki Itoh, Mototsugu Hamada. 702-707 [doi]
• An approach to the RF-LSI design for ubiquitous communication appliancesYuichi Kado, Mitsuru Harada. 708-714 [doi]
• Improving scalability of model-checking for minimizing buffer requirements of synchronous dataflow graphsNan Guan, Zonghua Gu, Wang Yi, Ge Yu. 715-720 [doi]
• A reverse-encoding-based on-chip AHB bus tracer for efficient circular buffer utilizationFu-Ching Yang, Cheng-Lung Chiang, Ing-Jer Huang. 721-726 [doi]
• Analyzing and optimizing energy efficiency of algorithms on DVS systems a first step towards algorithmic energy minimizationTetsuo Yokoyama, Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada. 727-732 [doi]
• Novel task migration framework on configurable heterogeneous MPSoC platformsHao Shen, Frédéric Pétrot. 733-738 [doi]
• A novel Toffoli network synthesis algorithm for reversible logicYexin Zheng, Chao Huang. 739-744 [doi]
• A cycle-based synthesis algorithm for reversible logicZahra Sasanian, Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani. 745-750 [doi]
• Array like runtime reconfigurable MIMO detectors for 802.11n WLAN: a design case studyPankaj Bhagawat, Rajballav Dash, Gwan S. Choi. 751-756 [doi]
• Mapping method for dynamically reconfigurable architectureAkira Kuroda, Mayuko Koezuka, Hidenori Matsuzaki, Takashi Yoshikawa, Shigehiro Asano. 757-762 [doi]
• A criticality-driven microarchitectural three dimensional (3D) floorplannerSrinath Sridharan, Michael DeBole, Guangyu Sun, Yuan Xie, Vijaykrishnan Narayanan. 763-768 [doi]
• Self-adjusting constrained random stimulus generation using splitting evenness evaluation and XOR constraintsShujun Deng, Zhiqiu Kong, Jinian Bian, Yanni Zhao. 769-774 [doi]
• Diagnosing integrator leakage of single-bit first-order DeltaSigma modulator using DC inputXuan-Lun Huang, Chen-Yuan Yang, Jiun-Lang Huang. 775-780 [doi]
• Path selection for monitoring unexpected systematic timing effectsNicholas Callegari, Pouria Bastani, Li-C. Wang, Sreejit Chakravarty, Alexander Tetelbaum. 781-786 [doi]
• Design for burn-in test: a technique for burn-in thermal stability under die-to-die parameter variationsMesut Meterelliyoz, Kaushik Roy. 787-792 [doi]
• Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraintsThomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara. 793-798 [doi]
• Soft lists: a native index structure for NOR-flash-based embedded devicesLi-Pin Chang, Chen-Hui Hsu. 799-804 [doi]
• Energy-aware register file re-partitioning for clustered VLIW architecturesYingchao Zhao, Chun Jason Xue, Minming Li, Bessie Hu. 805-810 [doi]
• Memory subsystem simulation in software TLM/T modelsEric Cheung, Harry Hsieh, Felice Balarin. 811-816 [doi]
• Exact and fast L1 cache simulation for embedded systemsNobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki. 817-822 [doi]
• Accuracy-aware SRAM: a reconfigurable low power SRAM architecture for mobile multimedia applicationsMinki Cho, Jason Schlessman, Wayne Wolf, Saibal Mukhopadhyay. 823-828 [doi]
• High-speed low-power FinFET based domino logicSeid Hadi Rasouli, Hanpei Koike, Kaustav Banerjee. 829-834 [doi]
• A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memoriesM. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli. 835-840 [doi]
• An alternate design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspectiveJing Li, Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik Roy. 841-846 [doi]
• A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systemsCharles Augustine, Behtash Behin-Aein, Xuanyao Fong, Kaushik Roy. 847-852 [doi]
• Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architectureBao Liu. 853-858 [doi]
• Dependable VLSI: device, design and architecture: how should they cooperate?Shuichi Sakai, Hidetoshi Onodera, Hiroto Yasuura, James C. Hoe. 859-860 [doi]