A 3D prototyping chip based on a wafer-level stacking technology

Nobuaki Miyakawa. A 3D prototyping chip based on a wafer-level stacking technology. In Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009. pages 416-420, IEEE, 2009. [doi]

Abstract

Abstract is missing.