A 3D prototyping chip based on a wafer-level stacking technology

Nobuaki Miyakawa. A 3D prototyping chip based on a wafer-level stacking technology. In Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009. pages 416-420, IEEE, 2009. [doi]

@inproceedings{Miyakawa09,
  title = {A 3D prototyping chip based on a wafer-level stacking technology},
  author = {Nobuaki Miyakawa},
  year = {2009},
  doi = {10.1145/1509633.1509736},
  url = {http://doi.acm.org/10.1145/1509633.1509736},
  tags = {rule-based},
  researchr = {https://researchr.org/publication/Miyakawa09},
  cites = {0},
  citedby = {0},
  pages = {416-420},
  booktitle = {Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009},
  publisher = {IEEE},
  isbn = {978-1-4244-2748-2},
}