Rajesh Garg - researchr alias

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Viewing Publication 1 - 29 from 29

2012

Patch management automation for enterprise cloudHai Huang, Salman Baset, Chunqiang Tang, Ashu Gupta, K. N. Madhu Sudhan, Fazal Feroze, Rajesh Garg, Sumithra Ravichandran. noms 2012: 691-705 [doi]

2009

Low power and high performance sram design using bank-based selective forward body biasKalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri. glvlsi 2009: 441-444 [doi]

On-chip bidirectional wiring for heavily pipelined systems using network codingKalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri. iccd 2009: 131-136 [doi]

Selective Forward Body Bias for High Speed and Low Power SRAMsKalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri. jolpe, 5(2):185-195, 2009. [doi]

SEU hardened clock regeneration circuitsRajballav Dash, Rajesh Garg, Sunil P. Khatri, Gwan S. Choi. isqed 2009: 806-813 [doi]

Encoding Serial Graphical Data for Energy-Delay Product/Energy MinimizationSasidharan Ekambavanan, Rajesh Garg, Sunil P. Khatri, Krishna R. Narayanan. jolpe, 5(2):157-172, 2009. [doi]

3D simulation and analysis of the radiation tolerance of voltage scaled digital circuitRajesh Garg, Sunil P. Khatri. iccd 2009: 498-504 [doi]

Efficient analytical determination of the SEU-induced pulse shapeRajesh Garg, Sunil P. Khatri. aspdac 2009: 461-467 [doi]

Circuit-Level Design Approaches for Radiation-Hard Digital ElectronicsRajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan S. Choi. tvlsi, 17(6):781-792, 2009. [doi]

A PLL design based on a standing wave resonant oscillatorVinay Karkala, Kalyana C. Bollapalli, Rajesh Garg, Sunil P. Khatri. iccd 2009: 511-516 [doi]

A radiation tolerant Phase Locked Loop design for digital electronicsRajesh Kumar, Vinay Karkala, Rajesh Garg, Tanuj Jindal, Sunil P. Khatri. iccd 2009: 505-510 [doi]

A robust pulsed flip-flop and its use in enhanced scan designRajesh Kumar, Kalyana C. Bollapalli, Rajesh Garg, Tarun Soni, Sunil P. Khatri. iccd 2009: 97-102 [doi]

Design and implementation of a sub-threshold BFSK transmitterSuganth Paul, Rajesh Garg, Sunil P. Khatri, Sheila Vaidya. isqed 2009: 664-672 [doi]

2008

A fast, analytical estimator for the SEU-induced pulse width in combinational designsRajesh Garg, Charu Nagpal, Sunil P. Khatri. dac 2008: 918-923 [doi]

A Single-supply True Voltage Level ShifterRajesh Garg, Gagandeep Mallarapu, Sunil P. Khatri. date 2008: 979-984 [doi]

A novel, highly SEU tolerant digital circuit design approachRajesh Garg, Sunil P. Khatri. iccd 2008: 14-20 [doi]

Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs)Rajesh Garg, Peng Li, Sunil P. Khatri. iscas 2008: 1788-1791 [doi]

A lithography-friendly structured ASIC design approachSalman Gopalani, Rajesh Garg, Sunil P. Khatri, Mosong Cheng. glvlsi 2008: 315-320 [doi]

A Delay-efficient Radiation-hard Digital Design Approach Using CWSP ElementsCharu Nagpal, Rajesh Garg, Sunil P. Khatri. date 2008: 354-359 [doi]

Pipelined network of PLA based circuit designSuganth Paul, Rajesh Garg, Sunil P. Khatri. glvlsi 2008: 213-218 [doi]

A robust, fast pulsed flip-flop designArunprasad Venkatraman, Rajesh Garg, Sunil P. Khatri. glvlsi 2008: 119-122 [doi]

2007

A methodology for interconnect dimension determinationJeff L. Cobb, Rajesh Garg, Sunil P. Khatri. ispd 2007: 189-195 [doi]

Low Power UWB Transceiver Design Using Dynamic Voltage ScalingRajesh Garg, Chunjie Duan, Jinyun Zhang, Sinan Gezici. wcnc 2007: 1757-1762 [doi]

2006

On the Improvement of Statistical Static Timing AnalysisRajesh Garg, Nikhil Jayakumar, Sunil P. Khatri. iccd 2006: 37-42 [doi]

Generalized buffering of PTL logic stages using Boolean divisionRajesh Garg, Sunil P. Khatri. iscas 2006: [doi]

A design approach for radiation-hard digital electronicsRajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan Choi. dac 2006: 773-778 [doi]

A design flow to optimize circuit delay by using standard cells and PLAsRajesh Garg, Mario Sanchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri. glvlsi 2006: 217-222 [doi]

A PLA based asynchronous micropipelining approach for subthreshold circuit designNikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P. Khatri. dac 2006: 419-424 [doi]

CMOS Comparators for High-Speed and Low-Power ApplicationsEric Menendez, Dumezie Maduike, Rajesh Garg, Sunil P. Khatri. iccd 2006: 76-81 [doi]

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Publications by 'Rajesh Garg'

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