Table of Contents

• Technology, CAD tools, and designs for emerging 3D integration technologySyed M. Alam, Mike Ignatowski, Yuan Xie. 1-2 [doi]
• GLSVLSI 2008 invited/keynote talkTak H. Ning. 3-4 [doi]
• Temperature-insensitive synthesis using multi-vt librariesAndrea Calimera, Enrico Macii, Massimo Poncino, R. Iris Bahar. 5-10 [doi]
• A formula of STI cmp design ruleMin-Chun Tsai. 11-16 [doi]
• Considering possible opens in non-tree topology wire delay calculationPhilipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl. 17-22 [doi]
• Variational capacitance modeling using orthogonal polynomial methodJian Cui, Gengsheng Chen, Ruijing Shen, Sheldon X.-D. Tan, Wenjian Yu, Jiarong Tong. 23-28 [doi]
• NBTI-aware flip-flop characterization and designHamed Abrishami, Safar Hatami, Behnam Amelifard, Massoud Pedram. 29-34 [doi]
• On-die CMOS voltage droop detection and dynamiccompensationMatthew Seetharam A. Holtz, Seetharam Narasimhan, Swarup Bhunia. 35-40 [doi]
• Collaborative sensing of on-chip wire temperatures using interconnect based ring oscillatorsBasab Datta, Wayne Burleson. 41-46 [doi]
• A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chipDhruva Ghai, Saraju P. Mohanty, Elias Kougianos. 47-52 [doi]
• A GF(p) elliptic curve group operator resistant against side channel attacksSantosh Ghosh, Monjur Alam, Dipanwita Roy Chowdhury, Indranil Sengupta. 53-58 [doi]
• Reconfigurable solutions for very-long arithmetic with applications in cryptographyAmbrose Chu, Scott Miller, Mihai Sima. 59-64 [doi]
• Fast composite field S-box architectures for advanced encryption standardRenfei Liu, Keshab K. Parhi. 65-70 [doi]
• A table-based method for single-pass cache optimizationPablo Viana, Ann Gordon-Ross, Edna Barros, Frank Vahid. 71-76 [doi]
• Using unsatisfiable cores to debug multiple design errorsAndré Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler. 77-82 [doi]
• A novel test-data compression technique using application-aware bitmask and dictionary selection methodsKanad Basu, Prabhat Mishra. 83-88 [doi]
• HyMacs: hybrid memory access optimization based on custom-instruction schedulingKang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto. 89-94 [doi]
• Automated formal verification of scheduling with speculative code motionsYoungsik Kim, Nazanin Mansouri. 95-100 [doi]
• Statistical timing analysis of flip-flops considering codependent setup and hold timesSafar Hatami, Hamed Abrishami, Massoud Pedram. 101-106 [doi]
• Compressor trees for decimal partial product reductionIvan D. Castellanos, James E. Stine. 107-110 [doi]
• Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuitsJ. V. R. Ravindra, M. B. Srinivas. 111-114 [doi]
• A high-speed radix-4 multiplexer-based array multiplierDimitris Bekiaris, Kiamal Z. Pekmestzi, Christos A. Papachristou. 115-118 [doi]
• A robust, fast pulsed flip-flop designArunprasad Venkatraman, Rajesh Garg, Sunil P. Khatri. 119-122 [doi]
• A low leakage 9t sram cell for ultra-low power operationSheng Lin, Yong-Bin Kim, Fabrizio Lombardi. 123-126 [doi]
• New technique in design of active rf cmos mixers for low flicker noise and high conversion gainYarallah Koolivand, Seyed Morteza Alavi, Omid Shoaei. 127-130 [doi]
• Recursion flatteningGreg Stitt, Jason R. Villarreal. 131-134 [doi]
• Quick supply current waveform estimation at gate level using existed cell library informationMu-Shun Lee, Chin-Hsun Lin, Chien-Nan Jimmy Liu, Shih-Che Lin. 135-138 [doi]
• Coverage-driven automatic test generation for uml activity diagramsMingsong Chen, Prabhat Mishra, Dhrubajyoti Kalita. 139-142 [doi]
• Hardware/software partitioning with multi-version implementation explorationGreg Stitt. 143-146 [doi]
• Improving FPGA routability using network codingKanupriya Gulati, Sunil P. Khatri. 147-150 [doi]
• Impact of dummy filling techniques on interconnect capacitance and planarization in nano-scale process technologyArthur Nieuwoudt, Jamil Kawa, Yehia Massoud. 151-154 [doi]
• Energy saving for memory with loop scheduling and prefetchingMeikang Qiu, Jiande Wu. 155-158 [doi]
• A layout-aware analog synthesis procedure inclusive of dynamic module geometry selectionAlmitra Pradhan, Ranga Vemuri. 159-162 [doi]
• Delay driven AIG restructuring using slack budget managementAndrew C. Ling, Jianwen Zhu, Stephen Dean Brown. 163-166 [doi]
• An analytical approach to placement legalizationAndrey Ayupov, Alexander Marchenko, Vladimir Tiourin. 167-170 [doi]
• Simultaneous optimization of total power, crosstalk noise, and delay under uncertaintyN. Ranganathan, Upavan Gupta, Venkataraman Mahalingam. 171-176 [doi]
• Optimal sleep transistor synthesis under timing and area constraintsAshoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino. 177-182 [doi]
• Energy efficiency bounds of pulse-encoded busesKarthik Duraisami, Enrico Macii, Massimo Poncino. 183-188 [doi]
• Implementation of asynchronous pipeline circuits in multi-threshold CMOS technologiesRaghid Shreih, Maitham Shams. 189-194 [doi]
• On the design of customizable low-voltage common-gate LNA-mixer pair using current and charge reusing techniquesHamid Nejati, Tamer Ragheb, Yehia Massoud. 195-200 [doi]
• Verifying start-up conditions for a ring oscillatorMark R. Greenstreet, Suwen Yang. 201-206 [doi]
• A cost-efficient partially-parallel irregular LDPC decoder based on sum-delta message passing algorithmWen Ji, Yuta Abe, Takeshi Ikenaga, Satoshi Goto. 207-212 [doi]
• Pipelined network of PLA based circuit designSuganth Paul, Rajesh Garg, Sunil P. Khatri. 213-218 [doi]
• A low-power 12-bit 80MHz CMOS DAC using pseudo-segmentationChanyang Joo, Soojae Kim, Kwangsub Yoon. 219-222 [doi]
• GLSVLSI 2008 invited/keynote talkWayne Wolf. 223-224 [doi]
• SAT-based equivalence checking of threshold logic designs for nanotechnologiesYexin Zheng, Michael S. Hsiao, Chao Huang. 225-230 [doi]
• Pairwise decomposition of toffoli gates in a quantum circuitNathan O. Scott, Gerhard W. Dueck. 231-236 [doi]
• Design of defect tolerant tile-based QCA circuitsVamsi Vankamamidi, Fabrizio Lombardi. 237-242 [doi]
• A layout-aware physical design method for constructing feasible QCA circuitsMayur Bubna, Sudip Roy, Naresh Shenoy, Subhra Mazumdar. 243-248 [doi]
• A hybrid cmos/nano fpga architecture built fromprogrammable majority logic arraysHarika Manem, Peter C. Paliwoda, Garrett S. Rose. 249-254 [doi]
• A novel performance driven power gating based on distributed sleep transistor networkLiangpeng Guo, Yici Cai, Qiang Zhou, Le Kang, Xianlong Hong. 255-260 [doi]
• A practical repeater insertion flowNikolai Ryzhenko, Oleg Venger. 261-266 [doi]
• Criticality history guided FPGA placement algorithm for timing optimizationHao Li, Yue Zhuo. 267-272 [doi]
• A linear programming formulation for security-aware gate sizingKoustav Bhattacharya, Nagarajan Ranganathan. 273-278 [doi]
• On efficient generation of instruction sequences to test for delay defects in a processorSankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Suriyaprakash Natarajan. 279-284 [doi]
• NBTI resilient circuits using adaptive body biasingZhenyu Qi, Mircea R. Stan. 285-290 [doi]
• A tool flow for predicting system level timing failures due to interconnect reliability degradationJin Guo, Antonis Papanikolaou, Michele Stucchi, Kristof Croes, Zsolt Tokei, Francky Catthoor. 291-296 [doi]
• Statistically translating low-level error probabilities to increase the accuracy and efficiency of reliability simulations in hardware description languagesDrew C. Ness, David J. Lilja. 297-302 [doi]
• Improved ber performance in intra-chip rf/wireless interconnect systemsMd. Sajjad Rahaman, Masud Chowdhury. 303-308 [doi]
• Scalable and fault-tolerant network-on-chip design usingthe quartered recursive diagonal torus topologyXianfang Tan, Lei Zhang, Shankar Neelkrishnan, Mei Yang, Yingtao Jiang, Yulu Yang. 309-314 [doi]
• A lithography-friendly structured ASIC design approachSalman Gopalani, Rajesh Garg, Sunil P. Khatri, Mosong Cheng. 315-320 [doi]
• Efficient tree topology for FPGA interconnect networkZied Marrakchi, Hayder Mrabet, Emna Amouri, Habib Mehrez. 321-326 [doi]
• Assumers for high-speed single and multi-cycle on-chip interconnect with low repeater countCharbel J. Akl, Magdy A. Bayoumi. 327-332 [doi]
• Mlp neural network and on-line backpropagation learning implementation in a low-cost fpgaErnesto Ordoñez-Cardenas, René de Jesús Romero-Troncoso. 333-338 [doi]
• Fast bus waveform estimation at the presence of coupling noiseJingye Xu, Pervez Khaled, Masud H. Chowdhury. 339-342 [doi]
• Mesh-of-tree deterministic routing for network-on-chip architectureSantanu Kundu, Santanu Chattopadhyay. 343-346 [doi]
• Fpga-based hardware/software co-design for chirplet signal decompositionYufeng Lu, Erdal Oruklu, Jafar Saniie. 347-350 [doi]
• Trends in energy-efficiency and robustness using stochastic sensor network-on-a-chipGirish Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones. 351-354 [doi]
• Using reiterative LFSR based X-masking to increase output compression in presence of unknownsRichard Putman. 355-358 [doi]
• Efficient and optimal post-layout double-cut via insertion by network relaxation and min-cost maximum flowLun-Chun Wei, Hung-Ming Chen, Li-Da Huang, Sarah Songjie Xu. 359-362 [doi]
• Guided test generation for isolation and detection of embedded trojans in icsMainak Banga, Maheshwar Chandrasekar, Lei Fang, Michael S. Hsiao. 363-366 [doi]
• Electrical models for vertical carbon nanotube capacitorsMark M. Budnik, Eric W. Johnson, Joshua D. Wood. 367-370 [doi]
• In-order pulsed charge recycling in off-chip data busesKimish Patel, Wonbok Lee, Massoud Pedram. 371-374 [doi]
• An energy-aware co-simulation framework for the design of wireless sensor networksAndrea Acquaviva, Franco Fummi, Giovanni Perbellini, Davide Quaglia. 375-378 [doi]
• Phase-based cache reconfiguration for a highly-configurable two-level cache hierarchyAnn Gordon-Ross, Jeremy Lau, Brad Calder. 379-382 [doi]
• Instruction cache leakage reduction by changing register operands and using asymmetric sram cellsMaziar Goudarzi, Tohru Ishihara. 383-386 [doi]
• Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --Koichi Hamamoto, Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye. 387-390 [doi]
• Full-chip leakage current estimation based on statistical sampling techniquesShaobo Liu, Qinru Qiu, Qing Wu. 391-394 [doi]
• A low-power phase change memory based hybrid cache architecturePrasanth Mangalagiri, Karthik Sarpatwari, Aditya Yanamandra, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Osama Awadel Karim. 395-398 [doi]
• Exploiting frequent opcode locality for power efficient instruction cacheYen-Jen Chang. 399-402 [doi]
• Simultaneous optimization of memory configuration and code allocation for low power embedded systemsTadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura. 403-406 [doi]
• Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanismsPaulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, Dionatan S. Moura, André Inácio Reis, Renato P. Ribas. 407-410 [doi]
• FEKIS: a fast architecture-level thermal analyzer for online thermal regulationPu Liu, Sheldon X.-D. Tan, Wei Wu, Murli Tirumala. 411-416 [doi]
• An analytical model for the upper bound on temperature differences on a chipShervin Sharifi, Tajana Simunic Rosing. 417-422 [doi]
• Power management of variation aware chip multiprocessorsAbu Saad Papa, Madhu Mutyam. 423-428 [doi]
• Low-power clock distribution in a multilayer core 3d microprocessorVenkatesh Arunachalam, Wayne Burleson. 429-434 [doi]
• Energy efficient synchronization techniques for embedded architecturesCesare Ferri, Amber Viescas, Tali Moreshet, R. Iris Bahar, Maurice Herlihy. 435-440 [doi]
• 12bits 40mhz pipelined ADC with duty-correction circuitJaeyong Lee, Sungil Cho, Kwangsub Yoon. 441-444 [doi]
• Comparison of redundant architectures for two-step ADCsGian Nicola Angotzi, Massimo Barbaro, Paul G. A. Jespers. 445-450 [doi]
• Nonuniformly quantized min-sum decoder architecture for low-density parity-check codesDaesun Oh, Keshab K. Parhi. 451-456 [doi]
• Extended layered decoding of LDPC codesZhiqiang Cui, Zhongfeng Wang. 457-462 [doi]