J. V. R. Ravindra, M. B. Srinivas. Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits. In Vijay Narayanan, Zhiyuan Yan, Enrico Macii, Sanjukta Bhanja, editors, Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008. pages 111-114, ACM, 2008. [doi]
Abstract is missing.