Andrew C. Ling - researchr alias

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Viewing Publication 1 - 24 from 24

2022

The Groq Software-defined Scale-out Tensor Streaming Multiprocessor : From chips-to-systems architectural overviewDennis Abts, John Kim, Garrin Kimmell, Matthew Boyd, Kris Kang, Sahil Parmar, Andrew C. Ling, Andrew Bitar, Ibrahim Ahmed 0007, Jonathan Ross. hotchips 2022: 1-69 [doi]

Challenges/Opportunities to Enable Dependable Scale-out System with Groq Deterministic Tensor-Streaming ProcessorsDennis Abts, Ibrahim Ahmed 0007, Andrew Bitar, Matthew Boyd, John Kim, Garrin Kimmell, Andrew C. Ling. dsn 2022: 19-22 [doi]

2018

DLA: Compiler and FPGA Overlay for Neural Network Inference AccelerationMohamed S. Abdelfattah, David Han, Andrew Bitar, Roberto DiCecco, Shane O'Connell, Nitika Shanker, Joseph Chu, Ian Prins, Joshua Fender, Andrew C. Ling, Gordon R. Chiu. fpl 2018: 411-418 [doi]

Flexibility: FPGAs and CAD in Deep Learning AccelerationGordon R. Chiu, Andrew C. Ling, Davor Capalija, Andrew Bitar, Mohamed S. Abdelfattah. ispd 2018: 34-41 [doi]

Harnessing Numerical Flexibility for Deep Learning on FPGAsAndrew C. Ling, Mohamed S. Abdelfattah, Shane O'Connell, Andrew Bitar, David Han, Roberto DiCecco, Suchit Subhaschandra, Chris N. Johnson, Dmitry Denisenko, Joshua Fender, Gordon R. Chiu. HEART 2018: [doi]

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASICEriko Nurvitadhi, Jeffrey J. Cook, Asit Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Aravind Dasu, Sergey Shumarayev. fpl 2018: 106-110 [doi]

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only)Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Sergey Shumarayev, Aravind Dasu. fpga 2018: 287 [doi]

2017

2013

Harnessing the power of FPGAs using altera's OpenCL compilerDeshanand P. Singh, Tomasz S. Czajkowski, Andrew C. Ling. fpga 2013: 5-6 [doi]

2011

Toward Automated ECOs in FPGAsAndrew C. Ling, Stephen Dean Brown, Sean Safarpour, Jianwen Zhu. tcad, 30(1):18-30, 2011. [doi]

2010

Towards scalable placement for FPGAsHuimin Bian, Andrew C. Ling, Alexander Choong, Jianwen Zhu. fpga 2010: 147-156 [doi]

2009

Towards automated ECOs in FPGAsAndrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour. fpga 2009: 3-12 [doi]

2008

Scalable Synthesis and Clustering Techniques Using Decision DiagramsAndrew C. Ling, Jianwen Zhu, Stephen Dean Brown. tcad, 27(3):423-435, 2008. [doi]

Delay driven AIG restructuring using slack budget managementAndrew C. Ling, Jianwen Zhu, Stephen Dean Brown. glvlsi 2008: 163-166 [doi]

2007

BddCut: Towards Scalable Symbolic Cut EnumerationAndrew C. Ling, Jianwen Zhu, Stephen Dean Brown. aspdac 2007: 408-413 [doi]

FPGA PLB Architecture Evaluation and Area Optimization Techniques Using Boolean SatisfiabilityAndrew C. Ling, Deshanand P. Singh, Stephen Dean Brown. tcad, 26(7):1196-1210, 2007. [doi]

Incremental placement for structured ASICs using the transportation problemAndrew C. Ling, Deshanand P. Singh, Stephen Dean Brown. vlsi 2007: 172-177 [doi]

2005

FPGA technology mapping: a study of optimalityAndrew C. Ling, Deshanand P. Singh, Stephen Dean Brown. dac 2005: 427-432 [doi]

FPGA Logic Synthesis Using Quantified Boolean SatisfiabilityAndrew C. Ling, Deshanand P. Singh, Stephen Dean Brown. sat 2005: 444-450 [doi]

FPGA PLB Evaluation using Quantified Boolean SatisfiabilityAndrew C. Ling, Deshanand P. Singh, Stephen Dean Brown. fpl 2005: 19-24

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