Abstract is missing.
- Emerging application domains: research challenges and opportunities for FPGAsJason Helge Anderson. 1-2 [doi]
- Towards automated ECOs in FPGAsAndrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour. 3-12 [doi]
- Clock power reduction for virtex-5 FPGAsQiang Wang, Subodh Gupta, Jason Helge Anderson. 13-22 [doi]
- Choose-your-own-adventure routing: lightweight load-time defect avoidanceRaphael Rubin, André DeHon. 23-32 [doi]
- Architectural enhancements in Stratix-III:::TM::: and Stratix-IV:::TM:::David Lewis, Elias Ahmed, David Cashman, Tim Vanderhoek, Christopher Lane, Andy Lee, Philip Pan. 33-42 [doi]
- Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAsPaul Teehan, Guy G. Lemieux, Mark R. Greenstreet. 43-52 [doi]
- A comparison of via-programmable gate array logic cell circuitsThomas C. P. Chau, Philip Heng Wai Leong, Sam M. H. Ho, Brian P. W. Chan, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Xinan Wang. 53-62 [doi]
- A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generationDavid B. Thomas, Lee Howes, Wayne Luk. 63-72 [doi]
- A high-performance FPGA architecture for restricted boltzmann machinesDaniel L. Ly, Paul Chow. 73-82 [doi]
- A multi-fpga 10x-real-time high-speed search engine for a 5000-word vocabulary speech recognizerEdward C. Lin, Rob A. Rutenbar. 83-92 [doi]
- FPGA-based front-end electronics for positron emission tomographyMichael Haselman, Robert Miyaoka, Thomas K. Lewellen, Scott Hauck, Wendy McDougald, Don Dewitt. 93-102 [doi]
- Fpga-based face detection system using Haar classifiersJunguk Cho, Shahnam Mirzaei, Jason Oberg, Ryan Kastner. 103-112 [doi]
- A 17ps time-to-digital converter implemented in 65nm FPGA technologyClaudio Favi, Edoardo Charbon. 113-120 [doi]
- CMOS vs Nano: comrades or rivals?Russell Tessier, Mojy C. Chian, Steve Trimberger, Shinobu Fujita, André DeHon, Deming Chen. 121-122 [doi]
- Making good points: application-specific pareto-point generation for design space exploration using statistical methodsDavid Sheldon, Frank Vahid. 123-132 [doi]
- VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scalingJason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Ye, Wei Mark Fang, Jonathan Rose. 133-142 [doi]
- FPGA technology mapping with encoded libraries andstaged priority cutsAndrew A. Kennings, Kristofer Vorwerk, Arun Kundu, Val Pevzner, Andy Fox. 143-150 [doi]
- Scalable don t-care-based logic optimization and resynthesisAlan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Stephen Jang. 151-160 [doi]
- FPCNA: a field programmable carbon nanotube arrayChen Dong, Scott Chilstedt, Deming Chen. 161-170 [doi]
- Flexible multi-mode embedded floating-point unit for field programmable gate arraysYee Jern Chong, Sri Parameswaran. 171-180 [doi]
- Wirelength modeling for homogeneous and heterogeneous FPGA architectural developmentAlastair M. Smith, Steven J. E. Wilton, Joydip Das. 181-190 [doi]
- SPR: an architecture-adaptive CGRA mapping toolStephen Friedman, Allan Carroll, Brian Van Essen, Benjamin Ylvisaker, Carl Ebeling, Scott Hauck. 191-200 [doi]
- Synthesis of reconfigurable high-performance multicore systemsJason Cong, Karthik Gururaj, Guoling Han. 201-208 [doi]
- Intel® atom:::TM::: processor core made FPGA-synthesizablePerry H. Wang, Jamison D. Collins, Christopher T. Weaver, Blliappa Kuttanna, Shahram Salamian, Gautham N. Chinya, Ethan Schuchman, Oliver Schilling, Thorsten Doil, Sebastian Steibl, Hong Wang 0003. 209-218 [doi]
- Large-scale wire-speed packet classification on FPGAsWeirong Jiang, Viktor K. Prasanna. 219-228 [doi]
- Fast and scalable packet classification using perfect hash functionsViktor Pus, Jan Korenek. 229-236 [doi]
- SmartOpt: an industrial strength framework for logic synthesisStephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, Kevin Chung, Alan Mishchenko, Robert K. Brayton. 237-240 [doi]
- Cholesky decomposition using fused datapath synthesisSüleyman Sirri Demirsoy, Martin Langhammer. 241-244 [doi]
- Diagonal tracks in FPGAs: a performance evaluationSumanta Chaudhuri. 245-248 [doi]
- A high performance fpga-based implementation of position specific iterated blastServer Kasap, Khaled Benkrid, Ying Liu. 249-252 [doi]
- A communication architecture for complex runtime reconfigurable systems and its implementation on spartan-3 FPGAsDirk Koch, Christian Beckhoff, Jürgen Teich. 253-256 [doi]
- PERG-Rx: a hardware pattern-matching engine supporting limited regular expressionsJohnny Tsung Lin Ho, Guy G. Lemieux. 257-260 [doi]
- High-performance, energy-efficient platforms using in-socket FPGA acceleratorsLiu Ling, Neal Oliver, Chitlur Bhushan, Wang Qigang, Alvin Chen, Shen Wenbo, Yu Zhihong, Arthur Sheiman, Ian McCallum, Joseph Grecco, Henry Mitchel, Liu Dong, Prabhat Gupta. 261-264 [doi]
- HW/SW methodologies for synchronization in FPGA multiprocessorsAntonino Tumeo, Christian Pilato, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto. 265-268 [doi]
- Automatic bus macro placement for partially reconfigurable FPGA designsJeffrey M. Carver, Richard Neil Pittman, Alessandro Forin. 269-272 [doi]
- Bus mastering PCI express in an FPGARay Bittner. 273-276 [doi]
- Soft vector processors vs FPGA custom hardware: measuring and reducing the gapPeter Yiannacouras, J. Gregory Steffan, Jonathan Rose. 277 [doi]
- Data streaming and simd support for the microblaze architecturePaul E. Marks, Cameron D. Patterson. 277 [doi]
- Small scale multiprocessor soft IP (SSM IP): single FPGA chip area and performance evaluationXinyu Li, Omar Hammami. 278 [doi]
- Customizable bit-width in an OpenMP-based circuit design toolTimothy F. Beatty, Eric E. Aubanel, Kenneth B. Kent. 278 [doi]
- Revisiting bitwidth optimizationsJason Cong, Karthik Gururaj, Bin Liu, Chunyue Liu, Yi Zou, Zhiru Zhang, Sheng Zhou. 278 [doi]
- An intermediate hardware model with load/store unit for C to FPGAAkira Yamawaki, Masahiko Iwane. 279 [doi]
- N-port memory mapping for LUT-based FPGAsZuo Wang, Feng Shi, Qi Zuo, Weixing Ji, Mengxiao Liu. 279 [doi]
- A clustering framework for task partitioning based on function-level data usage analysisS. Arash Ostadzadeh, Roel Meeuws, Kamana Sigdel, Koen Bertels. 279 [doi]
- Parallel placement for FPGAs revisitedCristinel Ababei. 280 [doi]
- Simultaneous multi-channel data acquisition with variable sampling frequencies using a scalable adaptive synchronous controllerMohammed Abdallah, Omar S. Elkeelany, Ali Alouani. 281 [doi]
- Computation reuse in domain-specific optimization of signal recognitionMelina Demertzi, Pedro C. Diniz, Mary W. Hall, Anna C. Gilbert, Yi Wang. 281 [doi]
- Performance and power of cache-based reconfigurable computingAndrew Putnam, Susan J. Eggers, Dave Bennett, Eric Dellinger, Jeff Mason, Henry Styles, Prasanna Sundararajan, Ralph Wittig. 281 [doi]
- The input-aware dynamic adaptation of area and performance for reconfigurable acceleratorLike Yan, Gang Wang, Tianzhou Chen. 281 [doi]
- HMMer acceleration using systolic array based reconfigurable architectureYanteng Sun, Peng Li, Guochang Gu, Yuan Wen, Yuan Liu, Dong Liu. 282 [doi]
- Implementation of the reconfiguration port scheduling on the erlangen slot machineFlorian Dittmann, Elmar Weber, Norma Montealegre. 282 [doi]
- 32-bit floating-point FPGA gaussian eliminationBowei Zhang, Guochang Gu, Lin Sun, Yanxia Wu. 283-284 [doi]
- Streaming implementation of a sequential decompression algorithm on an FPGAGaurav Mittal, David Zaretsky, Prithviraj Banerjee. 283 [doi]
- FPGA implementation of real-time skin color detection with mean-based surface flatteningSeunghun Jin, Dongkyun Kim, Thien Cong Pham, Jae Wook Jeon. 283 [doi]
- FPGAs with time-division multiplexed wiring: an architectural exploration and area analysisRosemary M. Francis, Simon W. Moore. 285 [doi]
- A parallel/vectorized double-precision exponential core to accelerate computational science applicationsRobin Pottathuparambil, Ron Sass. 285 [doi]
- Impact and compensation of correlated process variation on ring oscillator based pufAbhranil Maiti, Patrick Schaumont. 285 [doi]
- A novel BIST approach for testing input/output buffers in FPGAsChen Lei, Zhang Zhi Quan, Wen Zhi Ping. 285 [doi]
- Measuring and modeling variabilityusing low-cost FPGAsMichael Brown, Cyrus Bazeghi, Matthew R. Guthaus, Jose Renau. 286 [doi]
- A novel minloop SB design to improve FPGA routabilityJIanDe Yu, Jinmei Lai. 286 [doi]
- 3D configuration caching for 2D FPGAsAlessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj. 286 [doi]
- High-performance, cost-effective heterogeneous 3D FPGA architecturesRoto Le, Sherief Reda, R. Iris Bahar. 286 [doi]
- Implementation of a genetic algorithm on a virtex-ii pro FPGAMichalis Vavouras, Kyprianos Papadimitriou, Ioannis Papaefstathiou. 287 [doi]
- Closed-loop modeling of power and temperature profiles of FPGAsKanupriya Gulati, Sunil P. Khatri, Peng Li. 287 [doi]