Süleyman Sirri Demirsoy - researchr alias

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Viewing Publication 1 - 18 from 18

2023

DASH: Asynchronous Hardware Data Processing ServicesNorman May, Daniel Ritter 0001, Andre Dossinger, Christian Faerber, Süleyman Sirri Demirsoy. cidr 2023: [doi]

2022

Bandwidth-optimal Relational Joins on FPGAsRobert Lasch, Mehdi Moghaddamfar, Norman May, Süleyman Sirri Demirsoy, Christian Färber, Kai-Uwe Sattler. edbt 2022: 1-13 [doi]

2020

Faster & strong: string dictionary compression using sampling and fast vectorized decompressionRobert Lasch, Ismail Oukid, Roman Dementiev, Norman May, Süleyman Sirri Demirsoy, Kai-Uwe Sattler. vldb, 29(6):1263-1285, 2020. [doi]

2019

Fast & Strong: The Case of Compressed String Dictionaries on Modern CPUsRobert Lasch, Ismail Oukid, Roman Dementiev, Norman May, Süleyman Sirri Demirsoy, Kai-Uwe Sattler. damon 2019: [doi]

2009

SoC framework for FPGA: A case study of LTE PUSCH receiverSüleyman Sirri Demirsoy, Kellie Marks. socc 2009: 29-32 [doi]

Cholesky decomposition using fused datapath synthesisSüleyman Sirri Demirsoy, Martin Langhammer. fpga 2009: 241-244 [doi]

2008

Session MA5: Programmable and reconfigurable architecturesSüleyman Sirri Demirsoy. acssc 2008: 151-152 [doi]

2006

A computationally efficient DAB bit-stream processorR. Kazazoglu, Süleyman Sirri Demirsoy, Izzet Kale, Richard C. S. Morling. iscas 2006: [doi]

A Low-Complexity Self-Calibrating Adaptive Quadrature ReceiverEdiz Çetin, Süleyman Sirri Demirsoy, Izzet Kale, Richard C. S. Morling. ahs 2006: 428-435 [doi]

2005

Synthesis of reconfigurable multiplier blocks: part - II algorithmSüleyman Sirri Demirsoy, Izzet Kale, Andrew G. Dempster. iscas 2005: 540-543 [doi]

Synthesis of reconfigurable multiplier blocks: part I - fundamentalsSüleyman Sirri Demirsoy, Izzet Kale, Andrew G. Dempster. iscas 2005: 536-539 [doi]

Efficient FPGA implementation of an adaptive IQ-imbalance corrector for communication receivers using reduced range multipliersEdiz Çetin, Süleyman Sirri Demirsoy, Izzet Kale, Richard C. S. Morling. eusipco 2005: 1-4 [doi]

2003

Reconfigurable implementation of recursive DCT kernels for reduced quantization noiseSüleyman Sirri Demirsoy, Robert Beck, Andrew G. Dempster, Izzet Kale. iscas 2003: 289-292 [doi]

Design guidelines for reconfigurable multiplier blocksSüleyman Sirri Demirsoy, Andrew G. Dempster, Izzet Kale. iscas 2003: 293-296 [doi]

2002

Power analysis of multiplier blocksSüleyman Sirri Demirsoy, Andrew G. Dempster, Izzet Kale. iscas 2002: 297-300 [doi]

New Recursive DCT Implementations with Goertzel filtersSüleyman Sirri Demirsoy, Robert Beck, Izzet Kale, Andrew G. Dempster. ijcomputing, 1(1):45-49, 2002. [doi]

Designing multiplier blocks with low logic depthAndrew G. Dempster, Süleyman Sirri Demirsoy, Izzet Kale. iscas 2002: 773-776 [doi]

2000

Transition analysis on FPGA for multiplier-block based FIR filter structuresSüleyman Sirri Demirsoy, Andrew G. Dempster, Izzet Kale. icecsys 2000: 862-865 [doi]

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