Table of Contents

• Keynote speakerHermann Eul. 3-4 [doi]
• Plenary presentation AJames O'Riordan. 5 [doi]
• Plenary presentation BLiang-Gee Chen. 6 [doi]
• A high-level compilation toolchain for heterogeneous systemsWayne Luk, José Gabriel de Figueiredo Coutinho, Timothy John Todman, Yuet Ming Lam, William G. Osborne, Kong Woei Susanto, Qiang Liu, W. S. Wong. 9-18 [doi]
• A multi-level simulation approach in a Simulink-based design tool for FPGAsMaurizio Tranchero, Leonardo Maria Reyneri. 19-22 [doi]
• Efficient runtime performance monitoring of FPGA-based applicationsJoseph M. Lancaster, Jeremy D. Buhler, Roger D. Chamberlain. 23-28 [doi]
• SoC framework for FPGA: A case study of LTE PUSCH receiverSüleyman Sirri Demirsoy, Kellie Marks. 29-32 [doi]
• Performance comparison of two low power wide tuning range VCOs in 90 nm CMOSSaiyu Ren, Ray Siferd. 35-38 [doi]
• A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillatorPing Lu, Danfeng Chen, Fan Ye, Junyan Ren. 39-42 [doi]
• A PVT-insensitive time-to-digital converter using fractional difference Vernier delay linesNan Xing, Heesoo Song, Deog Kyoon Jeong, Suhwan Kim. 43-46 [doi]
• Hardware implementation on PCB in tandem with FPGA and experimental validation of a novel true random binary generatorMarta Blaszczyk, Richard A. Guinee. 47-50 [doi]
• Dual-band CDR using a half-rate linear phase detectorChorng-Sii Hwang, Chun-Yung Cho, Chung-Chun Chen, Hen-Wai Tsao. 51-54 [doi]
• A novel high-efficiency partial-parallel context modeling architecture for EBCOT in JPEG2000Xin Zhao, Ahmet T. Erdogan, Tughrul Arslan. 57-60 [doi]
• Tuning instruction customisation for reconfigurable system-on-chipChun Hok Ho, Wayne Luk, Jakub Szefer, Ruby B. Lee. 61-64 [doi]
• Method for improving performance in online routing of reconfigurable nano architecturesMahtab Niknahad, Michael Hübner, Jürgen Becker. 65-68 [doi]
• Low-distortion double-sampling ΔΣ ADC using a direct-charge-transfer adderYan Wang, Gabor C. Temes. 71-74 [doi]
• Design of a 1.8V 8-bit 1GSPS cascaded-folding CMOS A/D converter based on a folder averaging techniqueDongheon Lee, Seunghun Kim, Jooho Hwang, Junho Moon, Minkyu Song. 79-82 [doi]
• A high resolution capacitance deviation-to-digital converter utilizing time stretchingManho Kim, Nan Xing, Dong-Yong Shin, Hyunjoong Lee, Suhwan Kim. 83-86 [doi]
• Adaptive energy-aware latency-constrained DVFS policy for MPSoCDiego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, Lionel Torres. 89-92 [doi]
• A configurable length, Fused Multiply-Add floating point unit for a VLIW processorVassilios A. Chouliaras, Konstantinos Manolopoulos, Dionysios I. Reisis. 93-96 [doi]
• Heterogeneous multi-core architectures with dynamically reconfigurable processors for WiMAX transmitterWei Han, Ying Yi, Xin Zhao, Mark Muir, Tughrul Arslan, Ahmet T. Erdogan. 97-100 [doi]
• Asymmetrical Write-assist for single-ended SRAM operationJihi-Yu Lin, Ming-Hsien Tu, Ming-Chien Tsai, Shyh-Jye Jou, Ching-Te Chuang. 101-104 [doi]
• Improving Operational transconductance Amplifier (OTA) gain-bandwidth tradeoff using gate-underlap MOSFETsAbhinav Kranti, G. Alastair Armstrong. 107-110 [doi]
• Design of a complementary folded-cascode operational amplifierBjörn Lipka, Ulrich Kleine, Christoph Scheytt, Klaus Schmalz. 111-114 [doi]
• A 2.1-mW 0.3V-1.0V wide locking range multiphase DLL using self-estimated SAR algorithmYi-Ming Chang, Ming-Hung Chang, Wei Hwang. 115-118 [doi]
• High-speed, energy-efficient 2-cycle Multiply-Accumulate architectureTung Thanh Hoang, Magnus Själander, Per Larsson-Edefors. 119-122 [doi]
• 54-65 GHz six port demodulatorVincent F. Fusco, Chuang Wang. 125-128 [doi]
• Ultra wideband 32-67GHz phase shift keyed modulatorVincent F. Fusco, Chuang Wang. 129-132 [doi]
• A linearized low-voltage oscillator-mixerTero Koivisto, Esa Tiiliharju. 133-136 [doi]
• A current bleeding mixer based on Gilbert-cell featuring LO amplificationKai Xuan, Kim Fung Tsang, Shu Chuen Lee, Wah Ching Lee. 137-140 [doi]
• When does Network-on-Chip bypassing make sense?Simon J. Hollis, Chris Jackson. 143-146 [doi]
• Power optimal Network-on-Chip interconnect designG. Vikas, Joy Kuri, Kuruvilla Varghese. 147-150 [doi]
• A flow regulator for On-Chip CommunicationZhonghai Lu, Dimitris Brachos, Axel Jantsch. 151-154 [doi]
• High throughput architecture for CLICHÉ Network on ChipMohamed A. Abd El ghany, Magdy A. El-Moursy, Mohammed Ismail. 155-158 [doi]
• A low-cost SOC debug platform based on on-chip test architecturesKuen-Jong Lee, Si-Yuan Liang, Alan P. Su. 161-164 [doi]
• Comparator testing in a flash A/D converterCristian E. Onete. 165-168 [doi]
• A prototype platform for system-on-chip ADC test and measurementBrendan Mullane, Vincent O'Brien, Ciaran MacNamee, Thomas Fleischmann. 169-172 [doi]
• A fully digital power supply noise thermometerMariagrazia Graziano, Marco Diego Vittori. 173-176 [doi]
• A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort in 0.18μm CMOSSeungWon Lee, Tae-Ho Kim, Jae Wook Yoo, Jin-Ku Kang. 179-182 [doi]
• A novel low power, variable resolution pipelined ADCMahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas. 183-186 [doi]
• Correlating op-amp circuit noise with device flicker (1/f) noise for analog design applicationsPurushothaman Srinivasan, Andrew Marshall. 191-194 [doi]
• Experimental analysis of substrate isolation techniques for RF-SOC integrationMarc Molina, Xavier Aragonès, José Luis González. 199-202 [doi]
• High-purity 56-66GHz quadrupler for V-band radio homodyne and heterodyne transceiver applicationsChuang Wang, Vincent F. Fusco. 203-205 [doi]
• An instruction set architecture independent design method for embedded OFDM-based software defined transmitterJui-Chieh Lin, Minja Hsieh, Ming-Jung Fan-Chiang, Chu Yu, Sao-Jie Chen, Yu Hen Hu. 207-210 [doi]
• JavaFlow - A Java dataflow machineRobert J. Ascott, Earl E. Swartzlander Jr.. 211-214 [doi]
• Performance analysis of compressed instruction sets on workloads targeted at mobile internet devicesChander Sudanthi, Mrinmoy Ghosh, Kevin Welton, Nigel C. Paver. 215-218 [doi]
• Improved write margin 6T-SRAM for low supply voltage applicationsFarshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Tuan Vu Cao. 223-226 [doi]
• Low-power multiplier design with row and column bypassingJin-Tai Yan, Zhi-Wei Chen. 227-230 [doi]
• FPGA-based verification methodology of SoC-type CMOS image signal processorYounsun Kim, Hong Sik Kim, R. Lee, Sungho Kang. 231-234 [doi]
• A speech recognition SoC based on ARM7-TDMI core and a MSAC co-processorHui Geng, Weiqian Liang, Ming Dong. 235-238 [doi]
• Support vector machine FPGA implementation for video shot boundary detection applicationChun F. Hsu, Mong-Kai Ku, Li-Yen Liu. 239-242 [doi]
• Adaptive admission control on the SpiNNaker MPSoCShufan Yang, Stephen B. Furber, Luis A. Plana. 243-246 [doi]
• Generic routing rules and a scalable access enhancement for the Network-on-Chip RECONNECTAlexander Fell, Prasenjit Biswas, Jugantor Chetia, S. K. Nandy, Ranjani Narayan. 251-254 [doi]
• Non-overlapping transition encoding for global on-chip interconnectXiaofei Guo, Shunting Lin, Wael Refai, Garrett S. Rose. 255-258 [doi]
• Smart-flooding: A novel scheme for fault-tolerant NoCsAzeez Sanusi, Magdy A. Bayoumi. 259-262 [doi]
• Modelling control systems in SystemC AMS - Benefits and limitationsPhilipp A. Hartmann, Philipp Reinkemeier, Achim Rettberg, Wolfgang Nebel. 263-266 [doi]
• Scalable and low power LDPC decoder design using high level algorithmic synthesisYang Sun, Joseph R. Cavallaro, Tai Ly. 267-270 [doi]
• A versatile fading simulator for on-chip verification of MIMO communication systemsSaeed Fouladi Fard, Amirhossein Alimohammad, Bruce F. Cockburn, Christian Schlegel. 271-274 [doi]
• Low power RS codec using cell-based reconfigurable processorAhmed O. El-Rayis, Xin Zhao, Tughrul Arslan, Ahmet T. Erdogan. 279-282 [doi]
• Neuro inspired reconfigurable architecture for hardware/software co-designArfan Ghani, Liam McDaid, Ammar Belatreche, Waqar Ahmed. 287-290 [doi]
• Capacitance change estimation for an immunosensor chipRyoko Hayashi, Vijay K. Jain. 291-294 [doi]
• RF-MEMS resonator design for parameter characterizationAmbarish Roy, Bradley P. Barber, Kanti Prasad. 295-298 [doi]
• A holistic design approach for systems on chipFranz Dielacher, Christian Vogel, Peter Singerl, Stefan Mendel, Andreas Wiesbauer. 301-306 [doi]
• Clocked semi-floating-gate ultra low-voltage inverting current mirrorYngvar Berg, Omid Mirmotahari. 307-310 [doi]
• Temperature behavior of combination selection based mismatch calibration with 65 nm CMOS technologyJoona Marku, Jonne Poikonen, Ari Paasio. 311-314 [doi]
• Clocked semi-floating-gate ultra low-voltage symmetric and bidirectional current mirrorYngvar Berg, Omid Mirmotahari. 315-318 [doi]
• Generic integer linear programming formulation for 3D IC partitioningIris Hui-Ru Jiang. 321-324 [doi]
• SPICE versus STA tools: Challenges and tips for better correlationTariq E. L. Motassadeq, Vijay Sarathi, Syed Thameem, Mohamed Nijam. 325-328 [doi]
• OAL: An obstacle-aware legalization in standard cell placement with displacement minimizationSheng Chou, Tsung-Yi Ho. 329-332 [doi]
• Automatic debugging of System-on-a-Chip designsFrank Rogin, Rolf Drechsler, Steffen Rülke. 333-336 [doi]
• Enhancement of grid-based spatially-correlated variability modeling for improving SSTA accuracyShinyu Ninomiya, Masanori Hashimoto. 337-340 [doi]
• A reconfigurable co-processor for GMM-based classifierWei Wang, Weiqian Liang. 343-346 [doi]
• NFA decomposition and multiprocessing architecture for parallel regular expression processingYongping Liu, Sakir Sezer, John V. McCanny. 347-350 [doi]
• DDR3 based lookup circuit for high-performance network processingXin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns. 351-354 [doi]
• Removal-Cost Method: An efficient voltage selection algorithm for multi-core platforms under PVTSohaib Majzoub, Resve Saleh, Steven J. E. Wilton, Rabab Kreidieh Ward. 357-360 [doi]
• Fast dynamic power estimation considering glitch filteringLei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler. 361-364 [doi]
• Variation aware low power buffered interconnect designAshok Narasimhan, Ramalingam Sridhar. 365-368 [doi]
• A low-power pairing-based cryptographic accelerator for embedded security applicationsTom English, Maurice Keller, Ka Lok Man, Emanuel M. Popovici, Michel P. Schellekens, William P. Marnane. 369-372 [doi]
• An adaptive congestion-aware routing algorithm for mesh network-on-chip platformPo-Tsang Huang, Wei Hwang. 375-378 [doi]
• A floorplan-aware interactive tool flow for NoC design and synthesisMohammad Reza Kakoee, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Ciprian Seiculescu, Luca Benini. 379-382 [doi]
• 2 based parallel pipeline FFT processor for MB-OFDM UWB systemNuo Li, Nick van der Meijs. 383-386 [doi]
• ASIC evaluation of ECHO hash functionLiang Lu, Máire O'Neill, Earl E. Swartzlander Jr.. 387-390 [doi]
• A DSL for the SegBus platformMoazzam Fareed Niazi, Khalid Latif 0002, Hannu Tenhunen, Tiberiu Seceleanu. 393-398 [doi]
• Accurate power estimation of hardware co-processors using system level simulationSumit Ahuja, Deepak Mathaikutty, Avinash Lakshminarayana, Sandeep K. Shukla. 399-402 [doi]
• Generating interacting synchronous and asynchronous designs from simulink descriptionsMaurizio Tranchero, Leonardo Maria Reyneri. 403-406 [doi]
• Tuning SoCs using the global dynamic critical pathHari Kannan, Mihai Budiu, John D. Davis, Girish Venkataramani. 407-411 [doi]
• High path-count multirate Rayleigh fading channel simulator with time-multiplexed datapathSaeed Fouladi Fard, Amirhossein Alimohammad, Bruce F. Cockburn, Christian Schlegel. 412-415 [doi]
• High-performance architecture of H.264 integer-pixel motion estimation IP for real-time 1080HD video CODECHoyoung Chang, Soojin Kim, Seonyoung Lee, Kyeongsoon Cho. 419-422 [doi]
• FPGA-based SoC for transcoding H264/AVC-SVC with low latency and high bitrate entropy codingMichael Guarisco, Hassan Rabah, Yves Berviller, Serge Weber, Said Belkouch. 423-426 [doi]
• Memory efficient programmable processor for bitstream processing and entropy decoding of multiple-standard high-bitrate HDTV video bitstreamsNorman Nolte, Sören Moch, Markus Kock, Peter Pirsch. 427-431 [doi]
• Pixel-Parallel SPIHT for frame memory compressionYongseok Jin, Hyuk-Jae Lee. 432-435 [doi]
• System-on-System (SoS) architecture for 3-D secure imagingSang-Jin Lee, Kyung-Chang Park, Yeon-Ho Kim, Yun-ki Hong, Younggap You, Kyoung-Rok Cho, Tae Won Cho, Kamran Eshraghian. 436-439 [doi]
• Designing multi-processor Systems-on-ChipChristian Haubelt. 443 [doi]
• Microwave IC design for broadband receiversLiam M. Devlin. 444 [doi]
• Design in the nano-scale Era: Low-power, reliability, and error resiliencyKaushik Roy. 445 [doi]
• Introduction to the SystemC AMS DRAFT standardKarsten Einwich, Christoph Grimm, Martin Barnasconi, Alain Vachoux. 446 [doi]